hubio.h

umon bootloader source code, support mips cpu.

/*
 * Values for field reqtype.
 */
/* XXX - Need to fix this for Hub 2 */
#define	IIO_ICRB_REQ_DWRD	0	/* Request type double word	*/
#define	IIO_ICRB_REQ_QCLRD	1	/* Request is Qrtr Caceh line Rd */
#define	IIO_ICRB_REQ_BLKRD	2	/* Request is block read	*/
#define	IIO_ICRB_REQ_RSHU	6	/* Request is BTE block read	*/
#define	IIO_ICRB_REQ_REXU	7	/* request is BTE Excl Read	*/
#define	IIO_ICRB_REQ_RDEX	8	/* Request is Read Exclusive	*/
#define	IIO_ICRB_REQ_WINC	9	/* Request is Write Invalidate 	*/
#define	IIO_ICRB_REQ_BWINV	10	/* Request is BTE Winv		*/
#define	IIO_ICRB_REQ_PIORD	11	/* Request is PIO read		*/
#define	IIO_ICRB_REQ_PIOWR	12	/* Request is PIO Write 	*/
#define	IIO_ICRB_REQ_PRDM	13	/* Request is Fetch&Op		*/
#define	IIO_ICRB_REQ_PWRM	14	/* Request is Store &Op		*/
#define	IIO_ICRB_REQ_PTPWR	15	/* Request is Peer to peer	*/
#define	IIO_ICRB_REQ_WB		16	/* Request is Write back	*/
#define	IIO_ICRB_REQ_DEX	17	/* Retained DEX Cache line	*/

/*
 * Fields in CRB Register C
 */

#ifndef __ASSEMBLY__

typedef union icrbc_s {
	u64	reg_value;
	struct {
		u64	rsvd:	6,
			sleep:	1,
			pricnt: 4,	/* Priority count sent with Read req */
			pripsc: 4,	/* Priority Pre scalar 	*/
			bteop:	1,	/* BTE Operation 	*/
			push_be: 34,	/* Push address Byte enable
					 * Holds push addr, if CRB is for BTE
					 * If CRB belongs to Partial cache,
					 * this contains byte enables bits
					 * ([47:46] = 0)
					 */
			suppl:	11,	/* Supplemental field	*/
			barrop: 1,	/* Barrier Op bit set in xtalk req */
			doresp: 1,	/* Xtalk req needs a response 	*/
			gbr:	1;	/* GBR bit set in xtalk packet 	*/
	} icrbc_field_s;
} icrbc_t;

#define	c_pricnt	icrbc_field_s.pricnt
#define	c_pripsc	icrbc_field_s.pripsc
#define	c_bteop		icrbc_field_s.bteop
#define	c_bteaddr	icrbc_field_s.push_be	/* push_be field has 2 names */
#define c_benable 	icrbc_field_s.push_be	/* push_be field has 2 names */
#define	c_suppl		icrbc_field_s.suppl
#define	c_barrop	icrbc_field_s.barrop
#define	c_doresp	icrbc_field_s.doresp
#define	c_gbr	icrbc_field_s.gbr
#endif /* !__ASSEMBLY__ */

/*
 * Fields in CRB Register D
 */

#ifndef __ASSEMBLY__
typedef union icrbd_s {
	u64	reg_value;
	struct {
	    u64	rsvd:	38,
		toutvld: 1,	/* Timeout in progress for this CRB */
		ctxtvld: 1,	/* Context field below is valid	*/
		rsvd2:	1,
		context: 15, 	/* Bit vector:
				 * Has a bit set for each CRB entry
				 * which needs to be deallocated
				 * before this CRB entry is processed.
				 * Set only for barrier operations.
				 */
		timeout: 8;	/* Timeout Upper 8 bits	*/
	} icrbd_field_s;
} icrbd_t;

#define	icrbd_toutvld	icrbd_field_s.toutvld
#define	icrbd_ctxtvld	icrbd_field_s.ctxtvld
#define	icrbd_context	icrbd_field_s.context


typedef union hubii_ifdr_u {
	u64	hi_ifdr_value;
	struct {
		u64	ifdr_rsvd:	49,
	                ifdr_maxrp:	 7,
	                ifdr_rsvd1:	 1,
                      	ifdr_maxrq:	 7;
	} hi_ifdr_fields;
} hubii_ifdr_t;

#endif /* !__ASSEMBLY__ */

/*
 * Hardware designed names for the BTE control registers.
 */
#define IIO_IBLS_0	0x410000	/* BTE length/status 0 */
#define IIO_IBSA_0	0x410008	/* BTE source address 0 */
#define IIO_IBDA_0	0x410010	/* BTE destination address 0 */
#define IIO_IBCT_0	0x410018	/* BTE control/terminate 0 */
#define IIO_IBNA_0	0x410020	/* BTE notification address 0 */
#define IIO_IBNR_0	IIO_IBNA_0
#define IIO_IBIA_0	0x410028	/* BTE interrupt address 0 */

#define IIO_IBLS_1	0x420000	/* BTE length/status 1 */
#define IIO_IBSA_1	0x420008	/* BTE source address 1 */
#define IIO_IBDA_1	0x420010	/* BTE destination address 1 */
#define IIO_IBCT_1	0x420018	/* BTE control/terminate 1 */
#define IIO_IBNA_1	0x420020	/* BTE notification address 1 */
#define IIO_IBNR_1	IIO_IBNA_1
#define IIO_IBIA_1	0x420028	/* BTE interrupt address 1 */

/*
 * More miscellaneous registers
 */
#define IIO_IPCR	0x430000	/* Performance Control */
#define IIO_IPPR	0x430008	/* Performance Profiling */

/*
 * IO Error Clear register bit field definitions
 */
#define IECLR_BTE1		(1 << 18)  /* clear bte error 1 ??? */
#define IECLR_BTE0		(1 << 17)  /* clear bte error 0 ??? */
#define IECLR_CRAZY		(1 << 16)  /* clear crazy bit in wstat reg */
#define IECLR_PRB_F		(1 << 15)  /* clear err bit in PRB_F reg */
#define IECLR_PRB_E		(1 << 14)  /* clear err bit in PRB_E reg */
#define IECLR_PRB_D		(1 << 13)  /* clear err bit in PRB_D reg */
#define IECLR_PRB_C		(1 << 12)  /* clear err bit in PRB_C reg */
#define IECLR_PRB_B		(1 << 11)  /* clear err bit in PRB_B reg */
#define IECLR_PRB_A		(1 << 10)  /* clear err bit in PRB_A reg */
#define IECLR_PRB_9		(1 << 9)   /* clear err bit in PRB_9 reg */
#define IECLR_PRB_8		(1 << 8)   /* clear err bit in PRB_8 reg */
#define IECLR_PRB_0		(1 << 0)   /* clear err bit in PRB_0 reg */

/*
 * IO PIO Read Table Entry format
 */

#ifndef __ASSEMBLY__

typedef union iprte_a {
	u64	entry;
	struct {
	    u64	rsvd1     : 7,  /* Reserved field 		*/
		valid     : 1,	/* Maps to a timeout entry	*/
		rsvd2     : 1,
		srcnode   : 9,	/* Node which did this PIO	*/
		initiator : 2,	/* If T5A or T5B or IO 		*/
		rsvd3     : 3,
		addr      : 38,	/* Physical address of PIO	*/
		rsvd4     : 3;
	} iprte_fields;
} iprte_a_t;

#define	iprte_valid	iprte_fields.valid
#define	iprte_timeout	iprte_fields.timeout
#define	iprte_srcnode	iprte_fields.srcnode
#define	iprte_init	iprte_fields.initiator
#define	iprte_addr	iprte_fields.addr

#endif /* !__ASSEMBLY__ */

#define	IPRTE_ADDRSHFT	3

/*
 * Hub IIO PRB Register format.
 */

#ifndef __ASSEMBLY__
/*
 * Note: Fields bnakctr, anakctr, xtalkctrmode, ovflow fields are
 * "Status" fields, and should only be used in case of clean up after errors.
 */

typedef union iprb_u {
	u64	reg_value;
	struct {
	    u64	rsvd1:	15,
		error:	1,	/* Widget rcvd wr resp pkt w/ error */
		ovflow:	5,	/* Over flow count. perf measurement */
		fire_and_forget: 1, /* Launch Write without response */
		mode:	2,	/* Widget operation Mode	*/
		rsvd2:	2,
		bnakctr: 14,
		rsvd3: 	2,
		anakctr: 14,
		xtalkctr: 8;
	} iprb_fields_s;
} iprb_t;

#define iprb_regval	reg_value

#define	iprb_error	iprb_fields_s.error
#define	iprb_ovflow	iprb_fields_s.ovflow
#define	iprb_ff		iprb_fields_s.fire_and_forget
#define	iprb_mode	iprb_fields_s.mode
#define	iprb_bnakctr	iprb_fields_s.bnakctr
#define	iprb_anakctr	iprb_fields_s.anakctr
#define	iprb_xtalkctr	iprb_fields_s.xtalkctr

#endif /* !__ASSEMBLY__ */

/*
 * values for mode field in iprb_t.
 * For details of the meanings of NAK and Accept, refer the PIO flow
 * document
 */
#define	IPRB_MODE_NORMAL	(0)
#define	IPRB_MODE_COLLECT_A	(1)	/* PRB in collect A mode */
#define	IPRB_MODE_SERVICE_A	(2)	/* NAK B and Accept A */
#define	IPRB_MODE_SERVICE_B	(3)	/* NAK A and Accept B */

/*
 * IO CRB entry C_A to E_A : Partial (cache) CRBS
 */
#ifndef __ASSEMBLY__
typedef union icrbp_a {
	u64   ip_reg;	    /* the entire register value	*/
	struct {
	     u64 error:	1,  /*    63, error occurred		*/
		ln_uce:	1,  /*    62: uncorrectable memory 	*/
		ln_ae:	1,  /*    61: protection violation 	*/
		ln_werr:1,  /*    60: write access error 	*/
		ln_aerr:1,  /*    59: sn0net: Address error	*/
		ln_perr:1,  /*    58: sn0net: poison error	*/
		timeout:1,  /*    57: CRB timed out		*/
		l_bdpkt:1,  /*    56: truncated pkt on sn0net	*/
		c_bdpkt:1,  /*    55: truncated pkt on xtalk	*/
		c_err:	1,  /*    54: incoming xtalk req, err set*/
		rsvd1: 12,  /* 53-42: reserved			*/
		valid:	1,  /*    41: Valid status		*/
		sidn:	4,  /* 40-37: SIDN field of xtalk rqst	*/
		tnum:	5,  /* 36-32: TNUM of xtalk request	*/
		bo:	1,  /*    31: barrier op set in xtalk rqst*/
		resprqd:1,  /*    30: xtalk rqst requires response*/
		gbr:	1,  /*    29: gbr bit set in xtalk rqst	*/
		size:	2,  /* 28-27: size of xtalk request	*/
		excl:	4,  /* 26-23: exclusive bit(s)		*/
		stall:	3,  /* 22-20: stall (xtalk, bte 0/1)	*/
		intvn:	1,  /*    19: rqst target of intervention*/
		resp:	1,  /*    18: Data response given to t5	*/
		ack:	1,  /*    17: Data ack received.	*/
		hold:	1,  /*    16: crb gathering invalidate acks*/
		wb:	1,  /*    15: writeback pending.	*/
		ack_cnt:11, /* 14-04: counter of invalidate acks*/
		tscaler:4;  /* 03-00: Timeout prescaler		*/
	} ip_fmt;
} icrbp_a_t;

#endif /* !__ASSEMBLY__ */

/*
 * A couple of defines to go with the above structure.
 */
#define ICRBP_A_CERR_SHFT	54
#define ICRBP_A_ERR_MASK	0x3ff

#ifndef __ASSEMBLY__
typedef union hubii_idsr {
	u64 iin_reg;
	struct {
		u64 rsvd1 : 35,
	            isent : 1,
	            rsvd2 : 3,
	            ienable: 1,
	            rsvd  : 7,
	            node  : 9,
	            rsvd4 : 1,
	            level : 7;
	} iin_fmt;
} hubii_idsr_t;
#endif /* !__ASSEMBLY__ */

/*
 * IO BTE Length/Status (IIO_IBLS) register bit field definitions
 */
#define IBLS_BUSY		(0x1 << 20)
#define IBLS_ERROR_SHFT		16
#define IBLS_ERROR		(0x1 << IBLS_ERROR_SHFT)
#define IBLS_LENGTH_MASK	0xffff

/*
 * IO BTE Control/Terminate register (IBCT) register bit field definitions
 */
#define IBCT_POISON		(0x1 << 8)
#define IBCT_NOTIFY		(0x1 << 4)
#define IBCT_ZFIL_MODE		(0x1 << 0)

/*
 * IO BTE Interrupt Address Register (IBIA) register bit field definitions
 */
#define IBIA_LEVEL_SHFT		16
#define IBIA_LEVEL_MASK		(0x7f << IBIA_LEVEL_SHFT)
#define IBIA_NODE_ID_SHFT	0
#define IBIA_NODE_ID_MASK	(0x1ff)

/*
 * Miscellaneous hub constants
 */

/* Number of widgets supported by hub */
#define HUB_NUM_WIDGET		9
#define HUB_WIDGET_ID_MIN	0x8
#define HUB_WIDGET_ID_MAX	0xf

#define HUB_WIDGET_PART_NUM	0xc101
#define MAX_HUBS_PER_XBOW	2

/*
 * Get a hub's widget id from widget control register
 */
#define IIO_WCR_WID_GET(nasid)	(REMOTE_HUB_L(nasid, III_WCR) & 0xf)
#define IIO_WST_ERROR_MASK	(UINT64_CAST 1 << 32) /* Widget status error */

/*
 * Number of credits Hub widget has while sending req/response to
 * xbow.
 * Value of 3 is required by Xbow 1.1
 * We may be able to increase this to 4 with Xbow 1.2.
 */
#define       HUBII_XBOW_CREDIT       3
#define	      HUBII_XBOW_REV2_CREDIT  4

#endif /* _ASM_SGI_SN_SN0_HUBIO_H */