hubpi.h

umon bootloader source code, support mips cpu.

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Derived from IRIX <sys/SN/SN0/hubpi.h>, revision 1.28.
 *
 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
 * Copyright (C) 1999 by Ralf Baechle
 */
#ifndef	_ASM_SN_SN0_HUBPI_H
#define	_ASM_SN_SN0_HUBPI_H

#include <linux/types.h>

/*
 * Hub I/O interface registers
 *
 * All registers in this file are subject to change until Hub chip tapeout.
 * All register "addresses" are actually offsets.  Use the LOCAL_HUB
 * or REMOTE_HUB macros to synthesize an actual address
 */

#define PI_BASE			0x000000

/* General protection and control registers */

#define PI_CPU_PROTECT		0x000000 /* CPU Protection 		    */
#define PI_PROT_OVERRD		0x000008 /* Clear CPU Protection bit 	    */
#define	PI_IO_PROTECT		0x000010 /* Interrupt Pending Protection    */
#define PI_REGION_PRESENT	0x000018 /* Indicates whether region exists */
#define PI_CPU_NUM		0x000020 /* CPU Number ID 		    */
#define PI_CALIAS_SIZE		0x000028 /* Cached Alias Size 		    */
#define PI_MAX_CRB_TIMEOUT	0x000030 /* Maximum Timeout for CRB 	    */
#define PI_CRB_SFACTOR		0x000038 /* Scale factor for CRB timeout    */

/* CALIAS values */
#define PI_CALIAS_SIZE_0	0
#define PI_CALIAS_SIZE_4K	1
#define PI_CALIAS_SIZE_8K	2
#define PI_CALIAS_SIZE_16K	3
#define PI_CALIAS_SIZE_32K	4
#define PI_CALIAS_SIZE_64K	5
#define PI_CALIAS_SIZE_128K	6
#define PI_CALIAS_SIZE_256K	7
#define PI_CALIAS_SIZE_512K	8
#define PI_CALIAS_SIZE_1M	9
#define PI_CALIAS_SIZE_2M	10
#define PI_CALIAS_SIZE_4M	11
#define PI_CALIAS_SIZE_8M	12
#define PI_CALIAS_SIZE_16M	13
#define PI_CALIAS_SIZE_32M	14
#define PI_CALIAS_SIZE_64M	15

/* Processor control and status checking */

#define PI_CPU_PRESENT_A	0x000040 /* CPU Present A 		    */
#define PI_CPU_PRESENT_B	0x000048 /* CPU Present B 		    */
#define PI_CPU_ENABLE_A		0x000050 /* CPU Enable A 		    */
#define PI_CPU_ENABLE_B		0x000058 /* CPU Enable B 		    */
#define PI_REPLY_LEVEL		0x000060 /* Reply Level		 	    */
#define PI_HARDRESET_BIT	0x020068 /* Bit cleared by s/w on SR	    */
#define PI_NMI_A		0x000070 /* NMI to CPU A 		    */
#define PI_NMI_B		0x000078 /* NMI to CPU B 		    */
#define PI_NMI_OFFSET		(PI_NMI_B - PI_NMI_A)
#define PI_SOFTRESET		0x000080 /* Softreset (to both CPUs) 	    */

/* Regular Interrupt register checking.  */

#define PI_INT_PEND_MOD		0x000090 /* Write to set pending ints	    */
#define PI_INT_PEND0		0x000098 /* Read to get pending ints 	    */
#define PI_INT_PEND1		0x0000a0 /* Read to get pending ints 	    */
#define PI_INT_MASK0_A		0x0000a8 /* Interrupt Mask 0 for CPU A 	    */
#define PI_INT_MASK1_A		0x0000b0 /* Interrupt Mask 1 for CPU A 	    */
#define PI_INT_MASK0_B		0x0000b8 /* Interrupt Mask 0 for CPU B 	    */
#define PI_INT_MASK1_B		0x0000c0 /* Interrupt Mask 1 for CPU B 	    */

#define PI_INT_MASK_OFFSET	0x10	 /* Offset from A to B 		    */

/* Crosscall interrupts */

#define PI_CC_PEND_SET_A	0x0000c8 /* CC Interrupt Pending Set, CPU A */
#define PI_CC_PEND_SET_B	0x0000d0 /* CC Interrupt Pending Set, CPU B */
#define PI_CC_PEND_CLR_A	0x0000d8 /* CC Interrupt Pending Clr, CPU A */
#define PI_CC_PEND_CLR_B	0x0000e0 /* CC Interrupt Pending Clr, CPU B */
#define PI_CC_MASK		0x0000e8 /* CC Interrupt mask 		    */

#define PI_INT_SET_OFFSET	0x08	 /* Offset from A to B 		    */

/* Realtime Counter and Profiler control registers */

#define PI_RT_COUNT		0x030100 /* Real Time Counter 		    */
#define PI_RT_COMPARE_A		0x000108 /* Real Time Compare A 	    */
#define PI_RT_COMPARE_B		0x000110 /* Real Time Compare B 	    */
#define PI_PROFILE_COMPARE	0x000118 /* L5 int to both cpus when == RTC */
#define PI_RT_PEND_A		0x000120 /* Set if RT int for A pending     */
#define PI_RT_PEND_B		0x000128 /* Set if RT int for B pending     */
#define PI_PROF_PEND_A		0x000130 /* Set if Prof int for A pending   */
#define PI_PROF_PEND_B		0x000138 /* Set if Prof int for B pending   */
#define PI_RT_EN_A		0x000140 /* RT int for CPU A enable 	    */
#define PI_RT_EN_B		0x000148 /* RT int for CPU B enable 	    */
#define PI_PROF_EN_A		0x000150 /* PROF int for CPU A enable 	    */
#define PI_PROF_EN_B		0x000158 /* PROF int for CPU B enable 	    */
#define PI_RT_LOCAL_CTRL	0x000160 /* RT control register 	    */
#define PI_RT_FILTER_CTRL	0x000168 /* GCLK Filter control register    */

#define PI_COUNT_OFFSET		0x08	 /* A to B offset for all counts    */

/* Built-In Self Test support */

#define PI_BIST_WRITE_DATA	0x000200 /* BIST write data 		    */
#define PI_BIST_READ_DATA	0x000208 /* BIST read data 		    */
#define PI_BIST_COUNT_TARG	0x000210 /* BIST Count and Target 	    */
#define PI_BIST_READY		0x000218 /* BIST Ready indicator 	    */
#define PI_BIST_SHIFT_LOAD	0x000220 /* BIST control 		    */
#define PI_BIST_SHIFT_UNLOAD	0x000228 /* BIST control 		    */
#define PI_BIST_ENTER_RUN	0x000230 /* BIST control 		    */

/* Graphics control registers */

#define PI_GFX_PAGE_A		0x000300 /* Graphics page A 		    */
#define PI_GFX_CREDIT_CNTR_A	0x000308 /* Graphics credit counter A 	    */
#define PI_GFX_BIAS_A		0x000310 /* Graphics bias A 		    */
#define PI_GFX_INT_CNTR_A	0x000318 /* Graphics interrupt counter A    */
#define PI_GFX_INT_CMP_A	0x000320 /* Graphics interrupt comparator A */
#define PI_GFX_PAGE_B		0x000328 /* Graphics page B 		    */
#define PI_GFX_CREDIT_CNTR_B	0x000330 /* Graphics credit counter B 	    */
#define PI_GFX_BIAS_B		0x000338 /* Graphics bias B 		    */
#define PI_GFX_INT_CNTR_B	0x000340 /* Graphics interrupt counter B    */
#define PI_GFX_INT_CMP_B	0x000348 /* Graphics interrupt comparator B */

#define PI_GFX_OFFSET		(PI_GFX_PAGE_B - PI_GFX_PAGE_A)
#define PI_GFX_PAGE_ENABLE	0x0000010000000000LL

/* Error and timeout registers */
#define PI_ERR_INT_PEND		0x000400 /* Error Interrupt Pending	    */
#define PI_ERR_INT_MASK_A	0x000408 /* Error Interrupt mask for CPU A  */
#define PI_ERR_INT_MASK_B	0x000410 /* Error Interrupt mask for CPU B  */
#define PI_ERR_STACK_ADDR_A	0x000418 /* Error stack address for CPU A   */
#define PI_ERR_STACK_ADDR_B	0x000420 /* Error stack address for CPU B   */
#define PI_ERR_STACK_SIZE	0x000428 /* Error Stack Size 		    */
#define PI_ERR_STATUS0_A	0x000430 /* Error Status 0A 		    */
#define PI_ERR_STATUS0_A_RCLR	0x000438 /* Error Status 0A clear on read   */
#define PI_ERR_STATUS1_A	0x000440 /* Error Status 1A 		    */
#define PI_ERR_STATUS1_A_RCLR	0x000448 /* Error Status 1A clear on read   */
#define PI_ERR_STATUS0_B	0x000450 /* Error Status 0B 		    */
#define PI_ERR_STATUS0_B_RCLR	0x000458 /* Error Status 0B clear on read   */
#define PI_ERR_STATUS1_B	0x000460 /* Error Status 1B 		    */
#define PI_ERR_STATUS1_B_RCLR	0x000468 /* Error Status 1B clear on read   */
#define PI_SPOOL_CMP_A		0x000470 /* Spool compare for CPU A 	    */
#define PI_SPOOL_CMP_B		0x000478 /* Spool compare for CPU B 	    */
#define PI_CRB_TIMEOUT_A	0x000480 /* Timed out CRB entries for A     */
#define PI_CRB_TIMEOUT_B	0x000488 /* Timed out CRB entries for B     */
#define PI_SYSAD_ERRCHK_EN	0x000490 /* Enables SYSAD error checking    */
#define PI_BAD_CHECK_BIT_A	0x000498 /* Force SYSAD check bit error     */
#define PI_BAD_CHECK_BIT_B	0x0004a0 /* Force SYSAD check bit error     */
#define PI_NACK_CNT_A		0x0004a8 /* Consecutive NACK counter 	    */
#define PI_NACK_CNT_B		0x0004b0 /* 	"	" for CPU B 	    */
#define PI_NACK_CMP		0x0004b8 /* NACK count compare		    */
#define PI_STACKADDR_OFFSET	(PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A)
#define PI_ERRSTAT_OFFSET	(PI_ERR_STATUS0_B - PI_ERR_STATUS0_A)
#define PI_RDCLR_OFFSET		(PI_ERR_STATUS0_A_RCLR - PI_ERR_STATUS0_A)

/* Bits in PI_ERR_INT_PEND */
#define PI_ERR_SPOOL_CMP_B	0x00000001	/* Spool end hit high water */
#define PI_ERR_SPOOL_CMP_A	0x00000002
#define PI_ERR_SPUR_MSG_B	0x00000004	/* Spurious message intr.   */
#define PI_ERR_SPUR_MSG_A	0x00000008
#define PI_ERR_WRB_TERR_B	0x00000010	/* WRB TERR		    */
#define PI_ERR_WRB_TERR_A	0x00000020
#define PI_ERR_WRB_WERR_B	0x00000040	/* WRB WERR 		    */
#define PI_ERR_WRB_WERR_A	0x00000080
#define PI_ERR_SYSSTATE_B	0x00000100	/* SysState parity error    */
#define PI_ERR_SYSSTATE_A	0x00000200
#define PI_ERR_SYSAD_DATA_B	0x00000400	/* SysAD data parity error  */
#define PI_ERR_SYSAD_DATA_A	0x00000800
#define PI_ERR_SYSAD_ADDR_B	0x00001000	/* SysAD addr parity error  */
#define PI_ERR_SYSAD_ADDR_A	0x00002000
#define PI_ERR_SYSCMD_DATA_B	0x00004000	/* SysCmd data parity error */
#define PI_ERR_SYSCMD_DATA_A	0x00008000
#define PI_ERR_SYSCMD_ADDR_B	0x00010000	/* SysCmd addr parity error */
#define PI_ERR_SYSCMD_ADDR_A	0x00020000
#define PI_ERR_BAD_SPOOL_B	0x00040000	/* Error spooling to memory */
#define PI_ERR_BAD_SPOOL_A	0x00080000
#define PI_ERR_UNCAC_UNCORR_B	0x00100000	/* Uncached uncorrectable   */
#define PI_ERR_UNCAC_UNCORR_A	0x00200000
#define PI_ERR_SYSSTATE_TAG_B	0x00400000	/* SysState tag parity error */
#define PI_ERR_SYSSTATE_TAG_A	0x00800000
#define PI_ERR_MD_UNCORR	0x01000000	/* Must be cleared in MD    */

#define PI_ERR_CLEAR_ALL_A	0x00aaaaaa
#define PI_ERR_CLEAR_ALL_B	0x00555555


/*
 * The following three macros define all possible error int pends.
 */

#define PI_FATAL_ERR_CPU_A	(PI_ERR_SYSSTATE_TAG_A 	| \
				 PI_ERR_BAD_SPOOL_A 	| \
				 PI_ERR_SYSCMD_ADDR_A 	| \
				 PI_ERR_SYSCMD_DATA_A 	| \
				 PI_ERR_SYSAD_ADDR_A 	| \
				 PI_ERR_SYSAD_DATA_A	| \
				 PI_ERR_SYSSTATE_A)

#define PI_MISC_ERR_CPU_A	(PI_ERR_UNCAC_UNCORR_A 	| \
				 PI_ERR_WRB_WERR_A 	| \
				 PI_ERR_WRB_TERR_A 	| \
				 PI_ERR_SPUR_MSG_A 	| \
				 PI_ERR_SPOOL_CMP_A)

#define PI_FATAL_ERR_CPU_B	(PI_ERR_SYSSTATE_TAG_B 	| \
				 PI_ERR_BAD_SPOOL_B 	| \