tx4927.h

umon bootloader source code, support mips cpu.

/* TX4927 Timer 1 (32-bit registers) */
#define TX4927_TMR1_BASE                0xf100
#define TX4927_TMR1_TMTCR1              0xf104
#define TX4927_TMR1_TMTISR1             0xf108
#define TX4927_TMR1_TMCPRA1             0xf108
#define TX4927_TMR1_TMCPRB1             0xf10c
#define TX4927_TMR1_TMITMR1             0xf110
#define TX4927_TMR1_TMCCDR1             0xf120
#define TX4927_TMR1_TMPGMR1             0xf130
#define TX4927_TMR1_TMTRR1              0xf1f0
#define TX4927_TMR1_LIMIT               0xf1ff


/* TX4927 Timer 2 (32-bit registers) */
#define TX4927_TMR2_BASE                0xf200
#define TX4927_TMR2_TMTCR2              0xf104
#define TX4927_TMR2_TMTISR2             0xf208
#define TX4927_TMR2_TMCPRA2             0xf208
#define TX4927_TMR2_TMCPRB2             0xf20c
#define TX4927_TMR2_TMITMR2             0xf210
#define TX4927_TMR2_TMCCDR2             0xf220
#define TX4927_TMR2_TMPGMR2             0xf230
#define TX4927_TMR2_TMTRR2              0xf2f0
#define TX4927_TMR2_LIMIT               0xf2ff


/* TX4927 serial port 0 (32-bit registers) */
#define TX4927_SIO0_BASE                         0xf300 
#define TX4927_SIO0_SILCR0                       0xf300 
#define TX4927_SIO0_SILCR0_RESERVED_16_31                BM_16_31
#define TX4927_SIO0_SILCR0_RWUB                          BM_15_15
#define TX4927_SIO0_SILCR0_TWUB                          BM_14_14
#define TX4927_SIO0_SILCR0_UODE                          BM_13_13
#define TX4927_SIO0_SILCR0_RESERVED_07_12                BM_07_12
#define TX4927_SIO0_SILCR0_SCS                           BM_05_06
#define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_IC             (~BM_05_06)
#define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_BRG              BM_05_05
#define TX4927_SIO0_SILCR0_SCS_SCLK_EC                   BM_06_06
#define TX4927_SIO0_SILCR0_SCS_SCLK_BRG                  BM_05_06
#define TX4927_SIO0_SILCR0_UEPS                          BM_04_04
#define TX4927_SIO0_SILCR0_UPEN                          BM_03_03
#define TX4927_SIO0_SILCR0_USBL                          BM_02_02
#define TX4927_SIO0_SILCR0_UMODE                         BM_00_01
#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT              BM_00_01
#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT            (~BM_00_01)
#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC           BM_01_01
#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC           BM_00_01
#define TX4927_SIO0_SIDICR0                      0xf304 
#define TX4927_SIO0_SIDICR0_RESERVED_16_31               BM_16_31
#define TX4927_SIO0_SIDICR0_TDE                          BM_15_15
#define TX4927_SIO0_SIDICR0_RDE                          BM_14_14
#define TX4927_SIO0_SIDICR0_TIE                          BM_13_13
#define TX4927_SIO0_SIDICR0_RIE                          BM_12_12
#define TX4927_SIO0_SIDICR0_SPIE                         BM_11_11
#define TX4927_SIO0_SIDICR0_CTSAC                        BM_09_10
#define TX4927_SIO0_SIDICR0_CTSAC_NONE                 (~BM_09_10)
#define TX4927_SIO0_SIDICR0_CTSAC_RISE                   BM_09_09
#define TX4927_SIO0_SIDICR0_CTSAC_FALL                   BM_10_10
#define TX4927_SIO0_SIDICR0_CTSAC_BOTH                   BM_09_10
#define TX4927_SIO0_SIDICR0_RESERVED_06_08               BM_06_08
#define TX4927_SIO0_SIDICR0_STIE                         BM_00_05
#define TX4927_SIO0_SIDICR0_STIE_NONE                  (~BM_00_05)
#define TX4927_SIO0_SIDICR0_STIE_OERS                    BM_05_05
#define TX4927_SIO0_SIDICR0_STIE_CTSAC                   BM_04_04
#define TX4927_SIO0_SIDICR0_STIE_RBRKD                   BM_03_03
#define TX4927_SIO0_SIDICR0_STIE_TRDY                    BM_02_02
#define TX4927_SIO0_SIDICR0_STIE_TXALS                   BM_01_01
#define TX4927_SIO0_SIDICR0_STIE_UBRKD                   BM_00_00
#define TX4927_SIO0_SIDISR0                      0xf308 
#define TX4927_SIO0_SIDISR0_RESERVED_16_31               BM_16_31
#define TX4927_SIO0_SIDISR0_UBRK                         BM_15_15
#define TX4927_SIO0_SIDISR0_UVALID                       BM_14_14
#define TX4927_SIO0_SIDISR0_UFER                         BM_13_13
#define TX4927_SIO0_SIDISR0_UPER                         BM_12_12
#define TX4927_SIO0_SIDISR0_UOER                         BM_11_11
#define TX4927_SIO0_SIDISR0_ERI                          BM_10_10
#define TX4927_SIO0_SIDISR0_TOUT                         BM_09_09
#define TX4927_SIO0_SIDISR0_TDIS                         BM_08_08
#define TX4927_SIO0_SIDISR0_RDIS                         BM_07_07
#define TX4927_SIO0_SIDISR0_STIS                         BM_06_06
#define TX4927_SIO0_SIDISR0_RESERVED_05_05               BM_05_05
#define TX4927_SIO0_SIDISR0_RFDN                         BM_00_04
#define TX4927_SIO0_SISCISR0                     0xf30c 
#define TX4927_SIO0_SISCISR0_RESERVED_06_31              BM_06_31
#define TX4927_SIO0_SISCISR0_OERS                        BM_05_05
#define TX4927_SIO0_SISCISR0_CTSS                        BM_04_04
#define TX4927_SIO0_SISCISR0_RBRKD                       BM_03_03
#define TX4927_SIO0_SISCISR0_TRDY                        BM_02_02
#define TX4927_SIO0_SISCISR0_TXALS                       BM_01_01
#define TX4927_SIO0_SISCISR0_UBRKD                       BM_00_00
#define TX4927_SIO0_SIFCR0                       0xf310 
#define TX4927_SIO0_SIFCR0_RESERVED_16_31                BM_16_31
#define TX4927_SIO0_SIFCR0_SWRST                         BM_16_31
#define TX4927_SIO0_SIFCR0_RESERVED_09_14                BM_09_14
#define TX4927_SIO0_SIFCR0_RDIL                          BM_16_31
#define TX4927_SIO0_SIFCR0_RDIL_BYTES_1                (~BM_07_08)
#define TX4927_SIO0_SIFCR0_RDIL_BYTES_4                  BM_07_07
#define TX4927_SIO0_SIFCR0_RDIL_BYTES_8                  BM_08_08
#define TX4927_SIO0_SIFCR0_RDIL_BYTES_12                 BM_07_08
#define TX4927_SIO0_SIFCR0_RESERVED_05_06                BM_05_06
#define TX4927_SIO0_SIFCR0_TDIL                          BM_03_04
#define TX4927_SIO0_SIFCR0_TDIL_BYTES_1                (~BM_03_04)
#define TX4927_SIO0_SIFCR0_TDIL_BYTES_4                  BM_03_03
#define TX4927_SIO0_SIFCR0_TDIL_BYTES_8                  BM_04_04
#define TX4927_SIO0_SIFCR0_TDIL_BYTES_0                  BM_03_04
#define TX4927_SIO0_SIFCR0_TFRST                         BM_02_02
#define TX4927_SIO0_SIFCR0_RFRST                         BM_01_01
#define TX4927_SIO0_SIFCR0_FRSTE                         BM_00_00
#define TX4927_SIO0_SIFLCR0                      0xf314 
#define TX4927_SIO0_SIFLCR0_RESERVED_13_31               BM_13_31
#define TX4927_SIO0_SIFLCR0_RCS                          BM_12_12
#define TX4927_SIO0_SIFLCR0_TES                          BM_11_11
#define TX4927_SIO0_SIFLCR0_RESERVED_10_10               BM_10_10
#define TX4927_SIO0_SIFLCR0_RTSSC                        BM_09_09
#define TX4927_SIO0_SIFLCR0_RSDE                         BM_08_08
#define TX4927_SIO0_SIFLCR0_TSDE                         BM_07_07
#define TX4927_SIO0_SIFLCR0_RESERVED_05_06               BM_05_06
#define TX4927_SIO0_SIFLCR0_RTSTL                        BM_01_04
#define TX4927_SIO0_SIFLCR0_TBRK                         BM_00_00
#define TX4927_SIO0_SIBGR0                       0xf318 
#define TX4927_SIO0_SIBGR0_RESERVED_10_31                BM_10_31
#define TX4927_SIO0_SIBGR0_BCLK                          BM_08_09
#define TX4927_SIO0_SIBGR0_BCLK_T0                     (~BM_08_09)
#define TX4927_SIO0_SIBGR0_BCLK_T2                       BM_08_08
#define TX4927_SIO0_SIBGR0_BCLK_T4                       BM_09_09
#define TX4927_SIO0_SIBGR0_BCLK_T6                       BM_08_09
#define TX4927_SIO0_SIBGR0_BRD                           BM_00_07
#define TX4927_SIO0_SITFIF00                     0xf31c 
#define TX4927_SIO0_SITFIF00_RESERVED_08_31              BM_08_31
#define TX4927_SIO0_SITFIF00_TXD                         BM_00_07
#define TX4927_SIO0_SIRFIFO0                     0xf320          
#define TX4927_SIO0_SIRFIFO0_RESERVED_08_31              BM_08_31
#define TX4927_SIO0_SIRFIFO0_RXD                         BM_00_07
#define TX4927_SIO0_SIRFIFO0                     0xf320          
#define TX4927_SIO0_LIMIT                        0xf3ff 


/* TX4927 serial port 1 (32-bit registers) */
#define TX4927_SIO1_BASE                0xf400 
#define TX4927_SIO1_SILCR1              0xf400 
#define TX4927_SIO1_SIDICR1             0xf404 
#define TX4927_SIO1_SIDISR1             0xf408 
#define TX4927_SIO1_SISCISR1            0xf40c 
#define TX4927_SIO1_SIFCR1              0xf410 
#define TX4927_SIO1_SIFLCR1             0xf414 
#define TX4927_SIO1_SIBGR1              0xf418 
#define TX4927_SIO1_SITFIF01            0xf41c 
#define TX4927_SIO1_SIRFIFO1            0xf420 
#define TX4927_SIO1_LIMIT               0xf4ff 


/* TX4927 parallel port (32-bit registers) */
#define TX4927_PIO_BASE                 0xf500
#define TX4927_PIO_PIOD0                0xf500
#define TX4927_PIO_PIODI                0xf504
#define TX4927_PIO_PIODIR               0xf508
#define TX4927_PIO_PIOOD                0xf50c
#define TX4927_PIO_LIMIT                0xf50f


/* TX4927 Interrupt Controller (32-bit registers) */
#define TX4927_IRC_BASE                 0xf510
#define TX4927_IRC_IRFLAG0              0xf510
#define TX4927_IRC_IRFLAG1              0xf514
#define TX4927_IRC_IRPOL                0xf518
#define TX4927_IRC_IRRCNT               0xf51c
#define TX4927_IRC_IRMASKINT            0xf520
#define TX4927_IRC_IRMASKEXT            0xf524
#define TX4927_IRC_IRDEN                0xf600
#define TX4927_IRC_IRDM0                0xf604
#define TX4927_IRC_IRDM1                0xf608
#define TX4927_IRC_IRLVL0               0xf610
#define TX4927_IRC_IRLVL1               0xf614
#define TX4927_IRC_IRLVL2               0xf618
#define TX4927_IRC_IRLVL3               0xf61c
#define TX4927_IRC_IRLVL4               0xf620
#define TX4927_IRC_IRLVL5               0xf624
#define TX4927_IRC_IRLVL6               0xf628
#define TX4927_IRC_IRLVL7               0xf62c
#define TX4927_IRC_IRMSK                0xf640
#define TX4927_IRC_IREDC                0xf660
#define TX4927_IRC_IRPND                0xf680
#define TX4927_IRC_IRCS                 0xf6a0
#define TX4927_IRC_LIMIT                0xf6ff


/* TX4927 AC-link controller (32-bit registers) */
#define TX4927_ACLC_BASE                0xf700
#define TX4927_ACLC_ACCTLEN             0xf700
#define TX4927_ACLC_ACCTLDIS            0xf704
#define TX4927_ACLC_ACREGACC            0xf708
#define TX4927_ACLC_ACINTSTS            0xf710
#define TX4927_ACLC_ACINTMSTS           0xf714
#define TX4927_ACLC_ACINTEN             0xf718
#define TX4927_ACLC_ACINTDIS            0xf71c
#define TX4927_ACLC_ACSEMAPH            0xf720
#define TX4927_ACLC_ACGPIDAT            0xf740
#define TX4927_ACLC_ACGPODAT            0xf744
#define TX4927_ACLC_ACSLTEN             0xf748
#define TX4927_ACLC_ACSLTDIS            0xf74c
#define TX4927_ACLC_ACFIFOSTS           0xf750
#define TX4927_ACLC_ACDMASTS            0xf780
#define TX4927_ACLC_ACDMASEL            0xf784
#define TX4927_ACLC_ACAUDODAT           0xf7a0
#define TX4927_ACLC_ACSURRDAT           0xf7a4
#define TX4927_ACLC_ACCENTDAT           0xf7a8
#define TX4927_ACLC_ACLFEDAT            0xf7ac
#define TX4927_ACLC_ACAUDIDAT           0xf7b0
#define TX4927_ACLC_ACMODODAT           0xf7b8
#define TX4927_ACLC_ACMODIDAT           0xf7bc
#define TX4927_ACLC_ACREVID             0xf7fc
#define TX4927_ACLC_LIMIT               0xf7ff


#define TX4927_REG(x) ((TX4927_BASE)+(x))

#define TX4927_RD08( reg      )   (*(vu08*)(reg))
#define TX4927_WR08( reg, val )  ((*(vu08*)(reg))=(val))

#define TX4927_RD16( reg      )   (*(vu16*)(reg))
#define TX4927_WR16( reg, val )  ((*(vu16*)(reg))=(val))

#define TX4927_RD32( reg      )   (*(vu32*)(reg))
#define TX4927_WR32( reg, val )  ((*(vu32*)(reg))=(val))

#define TX4927_RD64( reg      )   (*(vu64*)(reg))
#define TX4927_WR64( reg, val )  ((*(vu64*)(reg))=(val))

#define TX4927_RD( reg      ) TX4927_RD32( reg )
#define TX4927_WR( reg, val ) TX4927_WR32( reg, val )





#define MI8259_IRQ_ISA_RAW_BEG   0    /* optional backplane i8259 */
#define MI8259_IRQ_ISA_RAW_END  15
#define TX4927_IRQ_CP0_RAW_BEG   0    /* tx4927 cpu built-in cp0 */
#define TX4927_IRQ_CP0_RAW_END   7
#define TX4927_IRQ_PIC_RAW_BEG   0    /* tx4927 cpu build-in pic */
#define TX4927_IRQ_PIC_RAW_END  31


#define MI8259_IRQ_ISA_BEG                          MI8259_IRQ_ISA_RAW_BEG   /*  0 */
#define MI8259_IRQ_ISA_END                          MI8259_IRQ_ISA_RAW_END   /* 15 */

#define TX4927_IRQ_CP0_BEG  ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_BEG)  /* 16 */
#define TX4927_IRQ_CP0_END  ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_END)  /* 23 */

#define TX4927_IRQ_PIC_BEG  ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_BEG)  /* 24 */
#define TX4927_IRQ_PIC_END  ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_END)  /* 55 */


#define TX4927_IRQ_USER0            (TX4927_IRQ_CP0_BEG+0)
#define TX4927_IRQ_USER1            (TX4927_IRQ_CP0_BEG+1)
#define TX4927_IRQ_NEST_PIC_ON_CP0  (TX4927_IRQ_CP0_BEG+2)
#define TX4927_IRQ_CPU_TIMER        (TX4927_IRQ_CP0_BEG+7)

#define TX4927_IRQ_NEST_EXT_ON_PIC  (TX4927_IRQ_PIC_BEG+3)

#endif /* __ASM_TX4927_TX4927_H */