sb1250_regs.h
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/* *********************************************************************
* SB1250 Board Support Package
*
* Register Definitions File: sb1250_regs.h
*
* This module contains the addresses of the on-chip peripherals
* on the SB1250.
*
* SB1250 specification level: 01/02/2002
*
* Author: Mitch Lichtenberg
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_REGS_H
#define _SB1250_REGS_H
#include "sb1250_defs.h"
/* *********************************************************************
* Some general notes:
*
* For the most part, when there is more than one peripheral
* of the same type on the SOC, the constants below will be
* offsets from the base of each peripheral. For example,
* the MAC registers are described as offsets from the first
* MAC register, and there will be a MAC_REGISTER() macro
* to calculate the base address of a given MAC.
*
* The information in this file is based on the SB1250 SOC
* manual version 0.2, July 2000.
********************************************************************* */
/* *********************************************************************
* Memory Controller Registers
********************************************************************* */
/*
* XXX: can't remove MC base 0 if 112x, since it's used by other macros,
* since there is one reg there (but it could get its addr/offset constant).
*/
#define A_MC_BASE_0 0x0010051000
#define A_MC_BASE_1 0x0010052000
#define MC_REGISTER_SPACING 0x1000
#define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0)
#define A_MC_REGISTER(ctlid,reg) (A_MC_BASE(ctlid)+(reg))
#define R_MC_CONFIG 0x0000000100
#define R_MC_DRAMCMD 0x0000000120
#define R_MC_DRAMMODE 0x0000000140
#define R_MC_TIMING1 0x0000000160
#define R_MC_TIMING2 0x0000000180
#define R_MC_CS_START 0x00000001A0
#define R_MC_CS_END 0x00000001C0
#define R_MC_CS_INTERLEAVE 0x00000001E0
#define S_MC_CS_STARTEND 16
#define R_MC_CSX_BASE 0x0000000200
#define R_MC_CSX_ROW 0x0000000000 /* relative to CSX_BASE, above */
#define R_MC_CSX_COL 0x0000000020 /* relative to CSX_BASE, above */
#define R_MC_CSX_BA 0x0000000040 /* relative to CSX_BASE, above */
#define MC_CSX_SPACING 0x0000000060 /* relative to CSX_BASE, above */
#define R_MC_CS0_ROW 0x0000000200
#define R_MC_CS0_COL 0x0000000220
#define R_MC_CS0_BA 0x0000000240
#define R_MC_CS1_ROW 0x0000000260
#define R_MC_CS1_COL 0x0000000280
#define R_MC_CS1_BA 0x00000002A0
#define R_MC_CS2_ROW 0x00000002C0
#define R_MC_CS2_COL 0x00000002E0
#define R_MC_CS2_BA 0x0000000300
#define R_MC_CS3_ROW 0x0000000320
#define R_MC_CS3_COL 0x0000000340
#define R_MC_CS3_BA 0x0000000360
#define R_MC_CS_ATTR 0x0000000380
#define R_MC_TEST_DATA 0x0000000400
#define R_MC_TEST_ECC 0x0000000420
#define R_MC_MCLK_CFG 0x0000000500
/* *********************************************************************
* L2 Cache Control Registers
********************************************************************* */
#define A_L2_READ_TAG 0x0010040018
#define A_L2_ECC_TAG 0x0010040038
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_L2_READ_MISC 0x0010040058
#endif /* 1250 PASS3 || 112x PASS1 */
#define A_L2_WAY_DISABLE 0x0010041000
#define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8))
#define A_L2_MGMT_TAG_BASE 0x00D0000000
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_L2_CACHE_DISABLE 0x0010042000
#define A_L2_MAKECACHEDISABLE(x) (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8))
#define A_L2_MISC_CONFIG 0x0010043000
#endif /* 1250 PASS2 || 112x PASS1 */
/* Backward-compatibility definitions. */
/* XXX: discourage people from using these constants. */
#define A_L2_READ_ADDRESS A_L2_READ_TAG
#define A_L2_EEC_ADDRESS A_L2_ECC_TAG
/* *********************************************************************
* PCI Interface Registers
********************************************************************* */
#define A_PCI_TYPE00_HEADER 0x00DE000000
#define A_PCI_TYPE01_HEADER 0x00DE000800
/* *********************************************************************
* Ethernet DMA and MACs
********************************************************************* */
#define A_MAC_BASE_0 0x0010064000
#define A_MAC_BASE_1 0x0010065000
#if SIBYTE_HDR_FEATURE_CHIP(1250)
#define A_MAC_BASE_2 0x0010066000
#endif /* 1250 */
#define MAC_SPACING 0x1000
#define MAC_DMA_TXRX_SPACING 0x0400
#define MAC_DMA_CHANNEL_SPACING 0x0100
#define DMA_RX 0
#define DMA_TX 1
#define MAC_NUM_DMACHAN 2 /* channels per direction */
/* XXX: not correct; depends on SOC type. */
#define MAC_NUM_PORTS 3
#define A_MAC_CHANNEL_BASE(macnum) \
(A_MAC_BASE_0 + \
MAC_SPACING*(macnum))
#define A_MAC_REGISTER(macnum,reg) \
(A_MAC_BASE_0 + \
MAC_SPACING*(macnum) + (reg))
#define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */
#define A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) \
((A_MAC_CHANNEL_BASE(macnum)) + \
R_MAC_DMA_CHANNELS + \
(MAC_DMA_TXRX_SPACING*(txrx)) + \
(MAC_DMA_CHANNEL_SPACING*(chan)))
#define R_MAC_DMA_CHANNEL_BASE(txrx,chan) \
(R_MAC_DMA_CHANNELS + \
(MAC_DMA_TXRX_SPACING*(txrx)) + \
(MAC_DMA_CHANNEL_SPACING*(chan)))
#define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg) \
(A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) + \
(reg))
#define R_MAC_DMA_REGISTER(txrx,chan,reg) \
(R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \
(reg))
/*
* DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE
*/
#define R_MAC_DMA_CONFIG0 0x00000000
#define R_MAC_DMA_CONFIG1 0x00000008
#define R_MAC_DMA_DSCR_BASE 0x00000010
#define R_MAC_DMA_DSCR_CNT 0x00000018
#define R_MAC_DMA_CUR_DSCRA 0x00000020
#define R_MAC_DMA_CUR_DSCRB 0x00000028
#define R_MAC_DMA_CUR_DSCRADDR 0x00000030
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define R_MAC_DMA_OODPKTLOST_RX 0x00000038 /* rx only */
#endif /* 1250 PASS3 || 112x PASS1 */
/*
* RMON Counters
*/
#define R_MAC_RMON_TX_BYTES 0x00000000
#define R_MAC_RMON_COLLISIONS 0x00000008
#define R_MAC_RMON_LATE_COL 0x00000010
#define R_MAC_RMON_EX_COL 0x00000018
#define R_MAC_RMON_FCS_ERROR 0x00000020
#define R_MAC_RMON_TX_ABORT 0x00000028
/* Counter #6 (0x30) now reserved */
#define R_MAC_RMON_TX_BAD 0x00000038
#define R_MAC_RMON_TX_GOOD 0x00000040
#define R_MAC_RMON_TX_RUNT 0x00000048
#define R_MAC_RMON_TX_OVERSIZE 0x00000050
#define R_MAC_RMON_RX_BYTES 0x00000080
#define R_MAC_RMON_RX_MCAST 0x00000088
#define R_MAC_RMON_RX_BCAST 0x00000090
#define R_MAC_RMON_RX_BAD 0x00000098
#define R_MAC_RMON_RX_GOOD 0x000000A0
#define R_MAC_RMON_RX_RUNT 0x000000A8
#define R_MAC_RMON_RX_OVERSIZE 0x000000B0
#define R_MAC_RMON_RX_FCS_ERROR 0x000000B8
#define R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0
#define R_MAC_RMON_RX_CODE_ERROR 0x000000C8
#define R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0
/* Updated to spec 0.2 */
#define R_MAC_CFG 0x00000100
#define R_MAC_THRSH_CFG 0x00000108
#define R_MAC_VLANTAG 0x00000110
#define R_MAC_FRAMECFG 0x00000118
#define R_MAC_EOPCNT 0x00000120
#define R_MAC_FIFO_PTRS 0x00000130
#define R_MAC_ADFILTER_CFG 0x00000200
#define R_MAC_ETHERNET_ADDR 0x00000208
#define R_MAC_PKT_TYPE 0x00000210
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define R_MAC_ADMASK0 0x00000218
#define R_MAC_ADMASK1 0x00000220
#endif /* 1250 PASS3 || 112x PASS1 */
#define R_MAC_HASH_BASE 0x00000240
#define R_MAC_ADDR_BASE 0x00000280
#define R_MAC_CHLO0_BASE 0x00000300
#define R_MAC_CHUP0_BASE 0x00000320
#define R_MAC_ENABLE 0x00000400
#define R_MAC_STATUS 0x00000408
#define R_MAC_INT_MASK 0x00000410
#define R_MAC_TXD_CTL 0x00000420
#define R_MAC_MDIO 0x00000428
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define R_MAC_STATUS1 0x00000430
#endif /* 1250 PASS2 || 112x PASS1 */
#define R_MAC_DEBUG_STATUS 0x00000448
#define MAC_HASH_COUNT 8
#define MAC_ADDR_COUNT 8
#define MAC_CHMAP_COUNT 4
/* *********************************************************************
* DUART Registers
********************************************************************* */
#define R_DUART_NUM_PORTS 2
#define A_DUART 0x0010060000
#define A_DUART_REG(r)
#define DUART_CHANREG_SPACING 0x100
#define A_DUART_CHANREG(chan,reg) (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg))
#define R_DUART_CHANREG(chan,reg) (DUART_CHANREG_SPACING*(chan) + (reg))
#define R_DUART_MODE_REG_1 0x100
#define R_DUART_MODE_REG_2 0x110
#define R_DUART_STATUS 0x120
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