sb1250_ldt.h

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/*  *********************************************************************
    *  SB1250 Board Support Package
    *  
    *  LDT constants				File: sb1250_ldt.h
    *  
    *  This module contains constants and macros to describe 
    *  the LDT interface on the SB1250.  
    *  
    *  SB1250 specification level:  User's manual 1/02/02
    *  
    *  Author:  Mitch Lichtenberg
    *  
    *********************************************************************  
    *
    *  Copyright 2000,2001,2002,2003
    *  Broadcom Corporation. All rights reserved.
    *  
    *  This program is free software; you can redistribute it and/or 
    *  modify it under the terms of the GNU General Public License as 
    *  published by the Free Software Foundation; either version 2 of 
    *  the License, or (at your option) any later version.
    *
    *  This program is distributed in the hope that it will be useful,
    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    *  GNU General Public License for more details.
    *
    *  You should have received a copy of the GNU General Public License
    *  along with this program; if not, write to the Free Software
    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
    *  MA 02111-1307 USA
    ********************************************************************* */


#ifndef _SB1250_LDT_H
#define _SB1250_LDT_H

#include "sb1250_defs.h"

#define K_LDT_VENDOR_SIBYTE	0x166D
#define K_LDT_DEVICE_SB1250	0x0002

/*
 * LDT Interface Type 1 (bridge) configuration header
 */

#define R_LDT_TYPE1_DEVICEID	0x0000
#define R_LDT_TYPE1_CMDSTATUS	0x0004
#define R_LDT_TYPE1_CLASSREV	0x0008
#define R_LDT_TYPE1_DEVHDR	0x000C
#define R_LDT_TYPE1_BAR0	0x0010	/* not used */
#define R_LDT_TYPE1_BAR1	0x0014	/* not used */

#define R_LDT_TYPE1_BUSID	0x0018	/* bus ID register */
#define R_LDT_TYPE1_SECSTATUS	0x001C	/* secondary status / I/O base/limit */
#define R_LDT_TYPE1_MEMLIMIT	0x0020
#define R_LDT_TYPE1_PREFETCH	0x0024
#define R_LDT_TYPE1_PREF_BASE	0x0028
#define R_LDT_TYPE1_PREF_LIMIT	0x002C
#define R_LDT_TYPE1_IOLIMIT	0x0030
#define R_LDT_TYPE1_CAPPTR	0x0034
#define R_LDT_TYPE1_ROMADDR	0x0038
#define R_LDT_TYPE1_BRCTL	0x003C
#define R_LDT_TYPE1_CMD		0x0040
#define R_LDT_TYPE1_LINKCTRL	0x0044
#define R_LDT_TYPE1_LINKFREQ	0x0048
#define R_LDT_TYPE1_RESERVED1	0x004C
#define R_LDT_TYPE1_SRICMD	0x0050
#define R_LDT_TYPE1_SRITXNUM	0x0054
#define R_LDT_TYPE1_SRIRXNUM	0x0058
#define R_LDT_TYPE1_ERRSTATUS   0x0068
#define R_LDT_TYPE1_SRICTRL	0x006C
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define R_LDT_TYPE1_ADDSTATUS	0x0070
#endif /* 1250 PASS2 || 112x PASS1 */
#define R_LDT_TYPE1_TXBUFCNT	0x00C8
#define R_LDT_TYPE1_EXPCRC	0x00DC
#define R_LDT_TYPE1_RXCRC	0x00F0


/*
 * LDT Device ID register
 */

#define S_LDT_DEVICEID_VENDOR		0
#define M_LDT_DEVICEID_VENDOR		_SB_MAKEMASK_32(16,S_LDT_DEVICEID_VENDOR)
#define V_LDT_DEVICEID_VENDOR(x)	_SB_MAKEVALUE_32(x,S_LDT_DEVICEID_VENDOR)
#define G_LDT_DEVICEID_VENDOR(x)	_SB_GETVALUE_32(x,S_LDT_DEVICEID_VENDOR,M_LDT_DEVICEID_VENDOR)

#define S_LDT_DEVICEID_DEVICEID		16
#define M_LDT_DEVICEID_DEVICEID		_SB_MAKEMASK_32(16,S_LDT_DEVICEID_DEVICEID)
#define V_LDT_DEVICEID_DEVICEID(x)	_SB_MAKEVALUE_32(x,S_LDT_DEVICEID_DEVICEID)
#define G_LDT_DEVICEID_DEVICEID(x)	_SB_GETVALUE_32(x,S_LDT_DEVICEID_DEVICEID,M_LDT_DEVICEID_DEVICEID)


/*
 * LDT Command Register (Table 8-13)
 */

#define M_LDT_CMD_IOSPACE_EN		_SB_MAKEMASK1_32(0)
#define M_LDT_CMD_MEMSPACE_EN		_SB_MAKEMASK1_32(1)
#define M_LDT_CMD_MASTER_EN		_SB_MAKEMASK1_32(2)
#define M_LDT_CMD_SPECCYC_EN		_SB_MAKEMASK1_32(3)
#define M_LDT_CMD_MEMWRINV_EN		_SB_MAKEMASK1_32(4)
#define M_LDT_CMD_VGAPALSNP_EN		_SB_MAKEMASK1_32(5)
#define M_LDT_CMD_PARERRRESP		_SB_MAKEMASK1_32(6)
#define M_LDT_CMD_WAITCYCCTRL		_SB_MAKEMASK1_32(7)
#define M_LDT_CMD_SERR_EN		_SB_MAKEMASK1_32(8)
#define M_LDT_CMD_FASTB2B_EN		_SB_MAKEMASK1_32(9)

/*
 * LDT class and revision registers
 */

#define S_LDT_CLASSREV_REV		0
#define M_LDT_CLASSREV_REV		_SB_MAKEMASK_32(8,S_LDT_CLASSREV_REV)
#define V_LDT_CLASSREV_REV(x)		_SB_MAKEVALUE_32(x,S_LDT_CLASSREV_REV)
#define G_LDT_CLASSREV_REV(x)		_SB_GETVALUE_32(x,S_LDT_CLASSREV_REV,M_LDT_CLASSREV_REV)

#define S_LDT_CLASSREV_CLASS		8
#define M_LDT_CLASSREV_CLASS		_SB_MAKEMASK_32(24,S_LDT_CLASSREV_CLASS)
#define V_LDT_CLASSREV_CLASS(x)		_SB_MAKEVALUE_32(x,S_LDT_CLASSREV_CLASS)
#define G_LDT_CLASSREV_CLASS(x)		_SB_GETVALUE_32(x,S_LDT_CLASSREV_CLASS,M_LDT_CLASSREV_CLASS)

#define K_LDT_REV			0x01
#define K_LDT_CLASS			0x060000

/*
 * Device Header (offset 0x0C)
 */

#define S_LDT_DEVHDR_CLINESZ		0
#define M_LDT_DEVHDR_CLINESZ		_SB_MAKEMASK_32(8,S_LDT_DEVHDR_CLINESZ)
#define V_LDT_DEVHDR_CLINESZ(x)		_SB_MAKEVALUE_32(x,S_LDT_DEVHDR_CLINESZ)
#define G_LDT_DEVHDR_CLINESZ(x)		_SB_GETVALUE_32(x,S_LDT_DEVHDR_CLINESZ,M_LDT_DEVHDR_CLINESZ)

#define S_LDT_DEVHDR_LATTMR		8
#define M_LDT_DEVHDR_LATTMR		_SB_MAKEMASK_32(8,S_LDT_DEVHDR_LATTMR)
#define V_LDT_DEVHDR_LATTMR(x)		_SB_MAKEVALUE_32(x,S_LDT_DEVHDR_LATTMR)
#define G_LDT_DEVHDR_LATTMR(x)		_SB_GETVALUE_32(x,S_LDT_DEVHDR_LATTMR,M_LDT_DEVHDR_LATTMR)

#define S_LDT_DEVHDR_HDRTYPE		16
#define M_LDT_DEVHDR_HDRTYPE		_SB_MAKEMASK_32(8,S_LDT_DEVHDR_HDRTYPE)
#define V_LDT_DEVHDR_HDRTYPE(x)		_SB_MAKEVALUE_32(x,S_LDT_DEVHDR_HDRTYPE)
#define G_LDT_DEVHDR_HDRTYPE(x)		_SB_GETVALUE_32(x,S_LDT_DEVHDR_HDRTYPE,M_LDT_DEVHDR_HDRTYPE)

#define K_LDT_DEVHDR_HDRTYPE_TYPE1	1

#define S_LDT_DEVHDR_BIST		24
#define M_LDT_DEVHDR_BIST		_SB_MAKEMASK_32(8,S_LDT_DEVHDR_BIST)
#define V_LDT_DEVHDR_BIST(x)		_SB_MAKEVALUE_32(x,S_LDT_DEVHDR_BIST)
#define G_LDT_DEVHDR_BIST(x)		_SB_GETVALUE_32(x,S_LDT_DEVHDR_BIST,M_LDT_DEVHDR_BIST)



/*
 * LDT Status Register (Table 8-14).  Note that these constants
 * assume you've read the command and status register 
 * together (32-bit read at offset 0x04)
 *
 * These bits also apply to the secondary status
 * register (Table 8-15), offset 0x1C
 */

#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_LDT_STATUS_VGAEN		_SB_MAKEMASK1_32(3)
#endif /* 1250 PASS2 || 112x PASS1 */
#define M_LDT_STATUS_CAPLIST		_SB_MAKEMASK1_32(20)
#define M_LDT_STATUS_66MHZCAP		_SB_MAKEMASK1_32(21)
#define M_LDT_STATUS_RESERVED2		_SB_MAKEMASK1_32(22)
#define M_LDT_STATUS_FASTB2BCAP		_SB_MAKEMASK1_32(23)
#define M_LDT_STATUS_MSTRDPARERR	_SB_MAKEMASK1_32(24)

#define S_LDT_STATUS_DEVSELTIMING	25
#define M_LDT_STATUS_DEVSELTIMING	_SB_MAKEMASK_32(2,S_LDT_STATUS_DEVSELTIMING)
#define V_LDT_STATUS_DEVSELTIMING(x)	_SB_MAKEVALUE_32(x,S_LDT_STATUS_DEVSELTIMING)
#define G_LDT_STATUS_DEVSELTIMING(x)	_SB_GETVALUE_32(x,S_LDT_STATUS_DEVSELTIMING,M_LDT_STATUS_DEVSELTIMING)

#define M_LDT_STATUS_SIGDTGTABORT	_SB_MAKEMASK1_32(27)
#define M_LDT_STATUS_RCVDTGTABORT	_SB_MAKEMASK1_32(28)
#define M_LDT_STATUS_RCVDMSTRABORT	_SB_MAKEMASK1_32(29)
#define M_LDT_STATUS_SIGDSERR		_SB_MAKEMASK1_32(30)
#define M_LDT_STATUS_DETPARERR		_SB_MAKEMASK1_32(31)

/*
 * Bridge Control Register (Table 8-16).  Note that these 
 * constants assume you've read the register as a 32-bit 
 * read (offset 0x3C)
 */

#define M_LDT_BRCTL_PARERRRESP_EN	_SB_MAKEMASK1_32(16)
#define M_LDT_BRCTL_SERR_EN		_SB_MAKEMASK1_32(17)
#define M_LDT_BRCTL_ISA_EN		_SB_MAKEMASK1_32(18)
#define M_LDT_BRCTL_VGA_EN		_SB_MAKEMASK1_32(19)
#define M_LDT_BRCTL_MSTRABORTMODE	_SB_MAKEMASK1_32(21)
#define M_LDT_BRCTL_SECBUSRESET		_SB_MAKEMASK1_32(22)
#define M_LDT_BRCTL_FASTB2B_EN		_SB_MAKEMASK1_32(23)
#define M_LDT_BRCTL_PRIDISCARD		_SB_MAKEMASK1_32(24)
#define M_LDT_BRCTL_SECDISCARD		_SB_MAKEMASK1_32(25)
#define M_LDT_BRCTL_DISCARDSTAT		_SB_MAKEMASK1_32(26)
#define M_LDT_BRCTL_DISCARDSERR_EN	_SB_MAKEMASK1_32(27)

/*
 * LDT Command Register (Table 8-17).  Note that these constants
 * assume you've read the command and status register together
 * 32-bit read at offset 0x40
 */

#define M_LDT_CMD_WARMRESET		_SB_MAKEMASK1_32(16)
#define M_LDT_CMD_DOUBLEENDED		_SB_MAKEMASK1_32(17)

#define S_LDT_CMD_CAPTYPE		29
#define M_LDT_CMD_CAPTYPE		_SB_MAKEMASK_32(3,S_LDT_CMD_CAPTYPE)