📄 mv643xx.h
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#define MV643XX_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
#define MV643XX_ETH_UNIT_INTERNAL_USE_REG 0x24fc
#define MV643XX_ETH_UNIT_ERROR_ADDR_REG 0x2094
#define MV643XX_ETH_BAR_0 0x2200
#define MV643XX_ETH_BAR_1 0x2208
#define MV643XX_ETH_BAR_2 0x2210
#define MV643XX_ETH_BAR_3 0x2218
#define MV643XX_ETH_BAR_4 0x2220
#define MV643XX_ETH_BAR_5 0x2228
#define MV643XX_ETH_SIZE_REG_0 0x2204
#define MV643XX_ETH_SIZE_REG_1 0x220c
#define MV643XX_ETH_SIZE_REG_2 0x2214
#define MV643XX_ETH_SIZE_REG_3 0x221c
#define MV643XX_ETH_SIZE_REG_4 0x2224
#define MV643XX_ETH_SIZE_REG_5 0x222c
#define MV643XX_ETH_HEADERS_RETARGET_BASE_REG 0x2230
#define MV643XX_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
#define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x2290
#define MV643XX_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
#define MV643XX_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
#define MV643XX_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
#define MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
#define MV643XX_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
#define MV643XX_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
#define MV643XX_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
#define MV643XX_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
#define MV643XX_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
#define MV643XX_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
#define MV643XX_ETH_DSCP_0(port) (0x2420 + (port<<10))
#define MV643XX_ETH_DSCP_1(port) (0x2424 + (port<<10))
#define MV643XX_ETH_DSCP_2(port) (0x2428 + (port<<10))
#define MV643XX_ETH_DSCP_3(port) (0x242c + (port<<10))
#define MV643XX_ETH_DSCP_4(port) (0x2430 + (port<<10))
#define MV643XX_ETH_DSCP_5(port) (0x2434 + (port<<10))
#define MV643XX_ETH_DSCP_6(port) (0x2438 + (port<<10))
#define MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
#define MV643XX_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
#define MV643XX_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
#define MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
#define MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
#define MV643XX_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
#define MV643XX_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
#define MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
#define MV643XX_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
#define MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
#define MV643XX_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
#define MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
#define MV643XX_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
#define MV643XX_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
#define MV643XX_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
#define MV643XX_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
#define MV643XX_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
#define MV643XX_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
#define MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
#define MV643XX_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
#define MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
#define MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
#define MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
/*******************************************/
/* CUNIT Registers */
/*******************************************/
/* Address Decoding Register Map */
#define MV64340_CUNIT_BASE_ADDR_REG0 0xf200
#define MV64340_CUNIT_BASE_ADDR_REG1 0xf208
#define MV64340_CUNIT_BASE_ADDR_REG2 0xf210
#define MV64340_CUNIT_BASE_ADDR_REG3 0xf218
#define MV64340_CUNIT_SIZE0 0xf204
#define MV64340_CUNIT_SIZE1 0xf20c
#define MV64340_CUNIT_SIZE2 0xf214
#define MV64340_CUNIT_SIZE3 0xf21c
#define MV64340_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240
#define MV64340_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244
#define MV64340_CUNIT_BASE_ADDR_ENABLE_REG 0xf250
#define MV64340_MPSC0_ACCESS_PROTECTION_REG 0xf254
#define MV64340_MPSC1_ACCESS_PROTECTION_REG 0xf258
#define MV64340_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C
/* Error Report Registers */
#define MV64340_CUNIT_INTERRUPT_CAUSE_REG 0xf310
#define MV64340_CUNIT_INTERRUPT_MASK_REG 0xf314
#define MV64340_CUNIT_ERROR_ADDR 0xf318
/* Cunit Control Registers */
#define MV64340_CUNIT_ARBITER_CONTROL_REG 0xf300
#define MV64340_CUNIT_CONFIG_REG 0xb40c
#define MV64340_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304
/* Cunit Debug Registers */
#define MV64340_CUNIT_DEBUG_LOW 0xf340
#define MV64340_CUNIT_DEBUG_HIGH 0xf344
#define MV64340_CUNIT_MMASK 0xf380
/* MPSCs Clocks Routing Registers */
#define MV64340_MPSC_ROUTING_REG 0xb400
#define MV64340_MPSC_RX_CLOCK_ROUTING_REG 0xb404
#define MV64340_MPSC_TX_CLOCK_ROUTING_REG 0xb408
/* MPSCs Interrupts Registers */
#define MV64340_MPSC_CAUSE_REG(port) (0xb804 + (port<<3))
#define MV64340_MPSC_MASK_REG(port) (0xb884 + (port<<3))
#define MV64340_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12))
#define MV64340_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12))
#define MV64340_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12))
#define MV64340_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12))
#define MV64340_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12))
#define MV64340_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12))
#define MV64340_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12))
#define MV64340_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12))
#define MV64340_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12))
#define MV64340_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12))
#define MV64340_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12))
#define MV64340_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12))
#define MV64340_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12))
/* MPSC0 Registers */
/***************************************/
/* SDMA Registers */
/***************************************/
#define MV64340_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13))
#define MV64340_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13))
#define MV64340_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13))
#define MV64340_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13))
#define MV64340_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13))
#define MV64340_SDMA_CAUSE_REG 0xb800
#define MV64340_SDMA_MASK_REG 0xb880
/* BRG Interrupts */
#define MV64340_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3))
#define MV64340_BRG_BAUDE_TUNING_REG(brg) (0xb208 + (brg<<3))
#define MV64340_BRG_CAUSE_REG 0xb834
#define MV64340_BRG_MASK_REG 0xb8b4
/****************************************/
/* DMA Channel Control */
/****************************************/
#define MV64340_DMA_CHANNEL0_CONTROL 0x840
#define MV64340_DMA_CHANNEL0_CONTROL_HIGH 0x880
#define MV64340_DMA_CHANNEL1_CONTROL 0x844
#define MV64340_DMA_CHANNEL1_CONTROL_HIGH 0x884
#define MV64340_DMA_CHANNEL2_CONTROL 0x848
#define MV64340_DMA_CHANNEL2_CONTROL_HIGH 0x888
#define MV64340_DMA_CHANNEL3_CONTROL 0x84C
#define MV64340_DMA_CHANNEL3_CONTROL_HIGH 0x88C
/****************************************/
/* IDMA Registers */
/****************************************/
#define MV64340_DMA_CHANNEL0_BYTE_COUNT 0x800
#define MV64340_DMA_CHANNEL1_BYTE_COUNT 0x804
#define MV64340_DMA_CHANNEL2_BYTE_COUNT 0x808
#define MV64340_DMA_CHANNEL3_BYTE_COUNT 0x80C
#define MV64340_DMA_CHANNEL0_SOURCE_ADDR 0x810
#define MV64340_DMA_CHANNEL1_SOURCE_ADDR 0x814
#define MV64340_DMA_CHANNEL2_SOURCE_ADDR 0x818
#define MV64340_DMA_CHANNEL3_SOURCE_ADDR 0x81c
#define MV64340_DMA_CHANNEL0_DESTINATION_ADDR 0x820
#define MV64340_DMA_CHANNEL1_DESTINATION_ADDR 0x824
#define MV64340_DMA_CHANNEL2_DESTINATION_ADDR 0x828
#define MV64340_DMA_CHANNEL3_DESTINATION_ADDR 0x82C
#define MV64340_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830
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