sdla_x25.h

umon bootloader source code, support mips cpu.

/*****************************************************************************
* sdla_x25.h	Sangoma X.25 firmware API definitions.
*
* Author:	Nenad Corbic	<[e-mail]>
*
* Copyright:	(c) 1995-2000 Sangoma Technologies Inc.
*
*		This program is free software; you can redistribute it and/or
*		modify it under the terms of the GNU General Public License
*		as published by the Free Software Foundation; either version
		2 of the License, or (at your option) any later version.
* ============================================================================
* Feb 28, 2000  Nenad Corbic    Updated for socket based x25api
* Dec 13, 1996	Gene Kozin	Initial version
*****************************************************************************/
#ifndef	_SDLA_X25_H
#define	_SDLA_X25_H

/*----------------------------------------------------------------------------
 * Notes:
 * ------
 * 1. All structures defined in this file are byte-alined.  
 *	Compiler	Platform	
 *	--------	--------
 *	GNU C		Linux
 *
 */

#ifndef	PACKED
#	define	PACKED	__attribute__((packed))
#endif	/* PACKED */

/******	CONSTANTS DEFINITIONS ***********************************************/

#define	X25_MAX_CHAN	255	/* max number of open X.25 circuits */
#define	X25_MAX_DATA	1024	/* max length of X.25 data buffer */
/*
 * X.25 shared memory layout.
 */
#define	X25_MBOX_OFFS	0x16B0	/* general mailbox block */
#define	X25_RXMBOX_OFFS	0x1AD0	/* receive mailbox */
#define	X25_STATUS_OFFS	0x1EF0	/* X.25 status structure */
#define X25_MB_VECTOR	0xE000	/* S514 mailbox window vecotr */
#define X25_MISC_HDLC_BITS 0x1F00 /*X.25 miscallaneous HDLC bits */

/* code levels */
#define HDLC_LEVEL 0x01
#define X25_LEVEL  0x02
#define X25_AND_HDLC_LEVEL 0x03
#define DO_HDLC_LEVEL_ERROR_CHECKING 0x04

/****** DATA STRUCTURES *****************************************************/

/*----------------------------------------------------------------------------
 * X.25 Command Block.
 */
typedef struct X25Cmd
{
	unsigned char command	PACKED;	/* command code */
	unsigned short length	PACKED;	/* transfer data length */
	unsigned char result	PACKED;	/* return code */
	unsigned char pf	PACKED;	/* P/F bit */
	unsigned short lcn	PACKED;	/* logical channel */
	unsigned char qdm	PACKED;	/* Q/D/M bits */
	unsigned char cause	PACKED;	/* cause field */
	unsigned char diagn	PACKED;	/* diagnostics */
	unsigned char pktType	PACKED;	/* packet type */
	unsigned char resrv[4]	PACKED;	/* reserved */
} TX25Cmd;

/*
 * Defines for the 'command' field.
 */
/*----- General commands --------------*/
#define X25_SET_GLOBAL_VARS	0x0B   	/* set global variables */ 
#define X25_READ_MODEM_STATUS	0x0C 	/* read modem status */
#define X25_READ_CODE_VERSION	0x15	/* read firmware version number */
#define X25_TRACE_CONFIGURE	0x14	/* configure trace facility */
#define X25_READ_TRACE_DATA	0x16	/* read trace data */
#define	X25_SET_INTERRUPT_MODE	0x17	/* set interrupt generation mode */
#define	X25_READ_INTERRUPT_MODE	0x18	/* read interrupt generation mode */
/*----- HDLC-level commands -----------*/
#define X25_HDLC_LINK_CONFIGURE	0x01	/* configure HDLC link level */   
#define X25_HDLC_LINK_OPEN	0x02	/* open HDLC link */         	
#define X25_HDLC_LINK_CLOSE	0x03	/* close HDLC link */
#define X25_HDLC_LINK_SETUP	0x04	/* set up HDLC link */ 
#define X25_HDLC_LINK_DISC	0x05	/* disconnect DHLC link */
#define X25_HDLC_LINK_STATUS	0x06	/* read DHLC link status */
#define X25_HDLC_READ_STATS	0x07	/* read operational statistics */
#define X25_HDLC_FLUSH_STATS	0x08 	/* flush operational statistics */
#define X25_HDLC_READ_COMM_ERR	0x09 	/* read error statistics */
#define X25_HDLC_FLUSH_COMM_ERR	0x0A	/* flush error statistics */
#define X25_HDLC_FLUSH_BUFFERS	0x0D	/* flush HDLC-level data buffers */
#define X25_HDLC_SPRVS_CNT_STAT 0x0F	/* read surervisory count status */
#define X25_HDLC_SEND_UI_FRAME	0x10	/* send unnumbered information frame */
#define X25_HDLC_WRITE		0x11	/* send HDLC information frame */
#define X25_HDLC_READ		0x21	/* read HDLC information frame */
#define X25_HDLC_READ_CONFIG	0x12	/* read HDLC configuration */
#define X25_HDLC_SET_CONFIG	0x13	/* set HDLC configuration */
#define SET_PROTOCOL_LEVEL	0x1F	/* set protocol level */
/*----- X.25-level commands -----------*/
#define X25_READ		0x22	/* read X.25 packet */
#define X25_WRITE		0x23	/* send X.25 packet */
#define X25_PLACE_CALL		0x30	/* place a call on SVC */
#define X25_ACCEPT_CALL		0x31	/* accept incomming call */
#define X25_CLEAR_CALL		0x32	/* clear call */
#define X25_CLEAR_CONFRM	0x33	/* send clear confirmation packet */
#define X25_RESET		0x34	/* send reset request packet */
#define X25_RESET_CONFRM	0x35	/* send reset confirmation packet */
#define X25_RESTART		0x36	/* send restart request packet */
#define X25_RESTART_CONFRM	0x37	/* send restart confirmation packet */
#define X25_INTERRUPT		0x38	/* send interrupt request packet */
#define X25_INTERRUPT_CONFRM	0x39	/* send interrupt confirmation pkt */
#define X25_REGISTRATION_RQST	0x3A	/* send registration request packet */
#define X25_REGISTRATION_CONFRM	0x3B	/* send registration confirmation */
#define X25_IS_DATA_AVAILABLE	0x40	/* querry receive queue */
#define X25_INCOMMING_CALL_CTL	0x41	/* select incomming call options */
#define X25_CONFIGURE_PVC	0x42	/* configure PVC */
#define X25_GET_ACTIVE_CHANNELS	0x43	/* get a list of active circuits */
#define X25_READ_CHANNEL_CONFIG	0x44	/* read virt. circuit configuration */
#define X25_FLUSH_DATA_BUFFERS	0x45	/* flush X.25-level data buffers */
#define X25_READ_HISTORY_TABLE	0x46	/* read asynchronous event log */
#define X25_HISTORY_TABLE_CTL	0x47	/* control asynchronous event log */
#define	X25_GET_TX_D_BIT_STATUS	0x48	/* is packet with D-bit acknowleged */
#define	X25_READ_STATISTICS	0x49	/* read X.25-level statistics */
#define	X25_FLUSH_STATISTICS	0x4A	/* flush X.25-level statistics */
#define	X25_READ_CONFIGURATION	0x50	/* read HDLC & X.25 configuration */
#define	X25_SET_CONFIGURATION	0x51	/* set HDLC & X.25 configuration */

/*
 * Defines for the 'result' field.
 */
/*----- General results ---------------*/
#define X25RES_OK		0x00
#define X25RES_ERROR		0x01
#define X25RES_LINK_NOT_IN_ABM	0x02	/* link is not in ABM mode */
#define X25RES_LINK_CLOSED	0x03
#define X25RES_INVAL_LENGTH	0x04
#define X25RES_INVAL_CMD	0x05
#define X25RES_UNNUMBERED_FRAME	0x06	/* unnunbered frame received */
#define X25RES_FRM_REJECT_MODE	0x07	/* link is in Frame Reject mode */
#define X25RES_MODEM_FAILURE	0x08	/* DCD and/or CTS dropped */
#define X25RES_N2_RETRY_LIMIT	0x09	/* N2 retry limit has been exceeded */
#define X25RES_INVAL_LCN	0x30	/* invalid logical channel number */
#define X25RES_INVAL_STATE	0x31	/* channel is not in data xfer mode */
#define X25RES_INVAL_DATA_LEN	0x32	/* invalid data length */
#define X25RES_NOT_READY	0x33	/* no data available / buffers full */
#define X25RES_NETWORK_DOWN	0x34
#define X25RES_CHANNEL_IN_USE	0x35	/* there is data queued on this LCN */
#define X25RES_REGST_NOT_SUPPRT	0x36	/* registration not supported */
#define X25RES_INVAL_FORMAT	0x37	/* invalid packet format */
#define X25RES_D_BIT_NOT_SUPPRT	0x38	/* D-bit pragmatics not supported */
#define X25RES_FACIL_NOT_SUPPRT	0x39	/* Call facility not supported */
#define X25RES_INVAL_CALL_ARG	0x3A	/* errorneous call arguments */
#define X25RES_INVAL_CALL_DATA	0x3B	/* errorneous call user data */
#define X25RES_ASYNC_PACKET	0x40	/* asynchronous packet received */
#define X25RES_PROTO_VIOLATION	0x41	/* protocol violation occurred */
#define X25RES_PKT_TIMEOUT	0x42	/* X.25 packet time out */
#define X25RES_PKT_RETRY_LIMIT	0x43	/* X.25 packet retry limit exceeded */
/*----- Command-dependent results -----*/
#define X25RES_LINK_DISC	0x00	/* HDLC_LINK_STATUS */
#define X25RES_LINK_IN_ABM	0x01	/* HDLC_LINK_STATUS */
#define X25RES_NO_DATA		0x01	/* HDLC_READ/READ_TRACE_DATA*/
#define X25RES_TRACE_INACTIVE	0x02	/* READ_TRACE_DATA */
#define X25RES_LINK_IS_OPEN	0x01	/* HDLC_LINK_OPEN */
#define X25RES_LINK_IS_DISC	0x02	/* HDLC_LINK_DISC */
#define X25RES_LINK_IS_CLOSED	0x03	/* HDLC_LINK_CLOSE */
#define X25RES_INVAL_PARAM	0x31	/* INCOMMING_CALL_CTL */
#define X25RES_INVAL_CONFIG	0x35	/* REGISTR_RQST/CONFRM */

/*
 * Defines for the 'qdm_bits' field.
 */
#define X25CMD_Q_BIT_MASK	0x04
#define X25CMD_D_BIT_MASK	0x02
#define X25CMD_M_BIT_MASK	0x01

/*
 * Defines for the 'pkt_type' field.
 */
/*----- Asynchronous events ------*/
#define ASE_CLEAR_RQST		0x02
#define ASE_RESET_RQST		0x04
#define ASE_RESTART_RQST	0x08
#define ASE_INTERRUPT		0x10
#define ASE_DTE_REGISTR_RQST	0x20
#define ASE_CALL_RQST		0x30
#define ASE_CALL_ACCEPTED	0x31
#define ASE_CLEAR_CONFRM	0x32
#define ASE_RESET_CONFRM	0x33
#define ASE_RESTART_CONFRM	0x34
#define ASE_INTERRUPT_CONFRM	0x35
#define ASE_DCE_REGISTR_CONFRM	0x36
#define ASE_DIAGNOSTIC		0x37
#define ASE_CALL_AUTO_CLEAR	0x38
#define AUTO_RESPONSE_FLAG	0x80
/*----- Time-Out events ----------*/
#define TOE_RESTART_RQST	0x03
#define TOE_CALL_RQST		0x05
#define TOE_CLEAR_RQST		0x08
#define TOE_RESET_RQST		0x0A
/*----- Protocol Violation events */
#define PVE_CLEAR_RQST		0x32
#define PVE_RESET_RQST		0x33
#define PVE_RESTART_RQST	0x34
#define PVE_DIAGNOSTIC		0x37

#define INTR_ON_RX_FRAME            0x01
#define INTR_ON_TX_FRAME            0x02
#define INTR_ON_MODEM_STATUS_CHANGE 0x04
#define INTR_ON_COMMAND_COMPLETE    0x08
#define INTR_ON_X25_ASY_TRANSACTION 0x10
#define INTR_ON_TIMER		    0x40
#define DIRECT_RX_INTR_USAGE        0x80

#define NO_INTR_PENDING  	        0x00
#define RX_INTR_PENDING			0x01	
#define TX_INTR_PENDING			0x02
#define MODEM_INTR_PENDING		0x04
#define COMMAND_COMPLETE_INTR_PENDING 	0x08
#define X25_ASY_TRANS_INTR_PENDING	0x10
#define TIMER_INTR_PENDING		0x40

/*----------------------------------------------------------------------------
 * X.25 Mailbox.
 *	This structure is located at offsets X25_MBOX_OFFS and X25_RXMBOX_OFFS
 *	into shared memory window.
 */
typedef struct X25Mbox
{
	unsigned char opflag	PACKED;	/* 00h: execution flag */
	TX25Cmd cmd		PACKED;	/* 01h: command block */
	unsigned char data[1]	PACKED;	/* 10h: data buffer */
} TX25Mbox;

/*----------------------------------------------------------------------------
 * X.25 Time Stamp Structure.
 */
typedef struct X25TimeStamp
{
	unsigned char month	PACKED;
	unsigned char date	PACKED;
	unsigned char sec	PACKED;
	unsigned char min	PACKED;
	unsigned char hour	PACKED;
} TX25TimeStamp;

/*----------------------------------------------------------------------------
 * X.25 Status Block.
 *	This structure is located at offset X25_STATUS_OFF into shared memory
 *	window.
 */
typedef struct X25Status
{
	unsigned short pvc_map	PACKED;	/* 00h: PVC map */
	unsigned short icc_map	PACKED;	/* 02h: Incomming Chan. map */
	unsigned short twc_map	PACKED;	/* 04h: Two-way Cnan. map */
	unsigned short ogc_map	PACKED;	/* 06h: Outgoing Chan. map */