📄 sed1356.h
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//------------------------------------------------------------------------
// sed1356.h: SED1356 LCD/CRT Controllers
//
#include "bits.h"
//------------------------------------------------------------------------
// cpu specific code must define the following board specific macros.
// Also the SED135x must be placed in the correct endian mode via
// hardware. Otherwise, the Macros must handle any address munging.
// #define SED_MEM_BASE 0xf0600000 <-- just example addresses,
// #define SED_REG_BASE 0xf0400000 <-- define for each board
// #define SED_STEP 1 <-- 1 = device is on 16-bit boundry, 2 = 32-bit boundry, 4 = 64-bit boundry
// #define SED_REG(_x_) *(vuchar *)(SED_REG_BASE + (_x_ * SED_STEP)) // Control/Status Registers
// #define RD_FB16(_reg_,_val_) ((_val_) = *((vushort *)((SED_MEM_BASE + (_reg_ * SED_STEP)))))
// #define WR_FB16(_reg_,_val_) (*((vushort *)((SED_MEM_BASE + (_reg_ * 2)))) = (_val_))
// SED1356 registers
#define SED_REG_REV SED_REG(0x00) // same for both 1355 and 1356
#define SED1356_REG_MISC SED_REG(0x01)
#define SED1356_REG_GPIO_CFG SED_REG(0x04)
#define SED1356_REG_GPIO_CTL SED_REG(0x08)
#define SED1356_REG_MD_CFG_RD_LO SED_REG(0x0c)
#define SED1356_REG_MD_CFG_RD_HI SED_REG(0x0d)
#define SED1356_REG_MCLK_CFG SED_REG(0x10)
#define SED1356_REG_LCD_PCLK_CFG SED_REG(0x14)
#define SED1356_REG_CRT_PCLK_CFG SED_REG(0x18)
#define SED1356_REG_MEDIA_PCLK_CFG SED_REG(0x1c)
#define SED1356_REG_WAIT_STATE SED_REG(0x1e)
#define SED1356_REG_MEM_CFG SED_REG(0x20)
#define SED1356_REG_REF_RATE SED_REG(0x21)
#define SED1356_REG_MEM_TMG0 SED_REG(0x2a)
#define SED1356_REG_MEM_TMG1 SED_REG(0x2b)
#define SED1356_REG_PANEL_TYPE SED_REG(0x30)
#define SED1356_REG_MOD_RATE SED_REG(0x31)
// LCD Control registers
#define SED1356_REG_LCD_HOR_DISP SED_REG(0x32)
#define SED1356_REG_LCD_HOR_NONDISP SED_REG(0x34)
#define SED1356_REG_LCD_HOR_START SED_REG(0x35)
#define SED1356_REG_LCD_HOR_PULSE SED_REG(0x36)
#define SED1356_REG_LCD_VER_DISP_HT_LO SED_REG(0x38)
#define SED1356_REG_LCD_VER_DISP_HT_HI SED_REG(0x39)
#define SED1356_REG_LCD_VER_NONDISP SED_REG(0x3a)
#define SED1356_REG_LCD_VER_START SED_REG(0x3b)
#define SED1356_REG_LCD_VER_PULSE SED_REG(0x3c)
#define SED1356_REG_LCD_DISP_MODE SED_REG(0x40)
#define SED1356_REG_LCD_MISC SED_REG(0x41)
#define SED1356_REG_LCD_DISP_START_LO SED_REG(0x42)
#define SED1356_REG_LCD_DISP_START_MID SED_REG(0x43)
#define SED1356_REG_LCD_DISP_START_HI SED_REG(0x44)
#define SED1356_REG_LCD_ADD_OFFSET_LO SED_REG(0x46)
#define SED1356_REG_LCD_ADD_OFFSET_HI SED_REG(0x47)
#define SED1356_REG_LCD_PIXEL_PAN SED_REG(0x48)
#define SED1356_REG_LCD_FIFO_HI_THRES SED_REG(0x4a)
#define SED1356_REG_LCD_FIFO_LO_THRES SED_REG(0x4b)
// CRT/TV Control registers
#define SED1356_REG_CRT_HOR_DISP SED_REG(0x50)
#define SED1356_REG_CRT_HOR_NONDISP SED_REG(0x52)
#define SED1356_REG_CRT_HOR_START SED_REG(0x53)
#define SED1356_REG_CRT_HOR_PULSE SED_REG(0x54)
#define SED1356_REG_CRT_VER_DISP_HT_LO SED_REG(0x56)
#define SED1356_REG_CRT_VER_DISP_HT_HI SED_REG(0x57)
#define SED1356_REG_CRT_VER_NONDISP SED_REG(0x58)
#define SED1356_REG_CRT_VER_START SED_REG(0x59)
#define SED1356_REG_CRT_VER_PULSE SED_REG(0x5a)
#define SED1356_REG_CRT_OUT_CTL SED_REG(0x5b)
#define SED1356_REG_CRT_DISP_MODE SED_REG(0x60)
#define SED1356_REG_CRT_DISP_START_LO SED_REG(0x62)
#define SED1356_REG_CRT_DISP_START_MID SED_REG(0x63)
#define SED1356_REG_CRT_DISP_START_HI SED_REG(0x64)
#define SED1356_REG_CRT_ADD_OFFSET_LO SED_REG(0x66)
#define SED1356_REG_CRT_ADD_OFFSET_HI SED_REG(0x67)
#define SED1356_REG_CRT_PIXEL_PAN SED_REG(0x68)
#define SED1356_REG_CRT_FIFO_HI_THRES SED_REG(0x6a)
#define SED1356_REG_CRT_FIFO_LO_THRES SED_REG(0x6b)
// LCD Cursor Control Registers
#define SED1356_REG_LCD_CURSOR_CTL SED_REG(0x70)
#define SED1356_REG_LCD_CURSOR_START_ADD SED_REG(0x71)
#define SED1356_REG_LCD_CURSOR_X_POS_LO SED_REG(0x72)
#define SED1356_REG_LCD_CURSOR_X_POS_HI SED_REG(0x73)
#define SED1356_REG_LCD_CURSOR_Y_POS_LO SED_REG(0x74)
#define SED1356_REG_LCD_CURSOR_Y_POS_HI SED_REG(0x75)
#define SED1356_REG_LCD_CURSOR_BLUE_CLR_0 SED_REG(0x76)
#define SED1356_REG_LCD_CURSOR_GREEN_CLR_0 SED_REG(0x77)
#define SED1356_REG_LCD_CURSOR_RED_CLR_0 SED_REG(0x78)
#define SED1356_REG_LCD_CURSOR_BLUE_CLR_1 SED_REG(0x7a)
#define SED1356_REG_LCD_CURSOR_GREEN_CLR_1 SED_REG(0x7b)
#define SED1356_REG_LCD_CURSOR_RED_CLR_1 SED_REG(0x7c)
#define SED1356_REG_LCD_CURSOR_FIFO_THRESH SED_REG(0x7e)
// CRT Cursor Control Registers
#define SED1356_REG_CRT_CURSOR_CTL SED_REG(0x80)
#define SED1356_REG_CRT_CURSOR_START_ADD SED_REG(0x81)
#define SED1356_REG_CRT_CURSOR_X_POS_LO SED_REG(0x82)
#define SED1356_REG_CRT_CURSOR_X_POS_HI SED_REG(0x83)
#define SED1356_REG_CRT_CURSOR_Y_POS_LO SED_REG(0x84)
#define SED1356_REG_CRT_CURSOR_Y_POS_HI SED_REG(0x85)
#define SED1356_REG_CRT_CURSOR_BLUE_CLR_0 SED_REG(0x86)
#define SED1356_REG_CRT_CURSOR_GREEN_CLR_0 SED_REG(0x87)
#define SED1356_REG_CRT_CURSOR_RED_CLR_0 SED_REG(0x88)
#define SED1356_REG_CRT_CURSOR_BLUE_CLR_1 SED_REG(0x8a)
#define SED1356_REG_CRT_CURSOR_GREEN_CLR_1 SED_REG(0x8b)
#define SED1356_REG_CRT_CURSOR_RED_CLR_1 SED_REG(0x8c)
#define SED1356_REG_CRT_CURSOR_FIFO_THRESH SED_REG(0x8e)
// BitBlt Control Registers
#define SED1356_REG_BLT_CTL_0 SED_REG(0x100)
#define SED1356_REG_BLT_CTL_1 SED_REG(0x101)
#define SED1356_REG_BLT_ROP_CODE SED_REG(0x102)
#define SED1356_REG_BLT_OP SED_REG(0x103)
#define SED1356_REG_BLT_SRC_START_LO SED_REG(0x104)
#define SED1356_REG_BLT_SRC_START_MID SED_REG(0x105)
#define SED1356_REG_BLT_SRC_START_HI SED_REG(0x106)
#define SED1356_REG_BLT_DEST_START_LO SED_REG(0x108)
#define SED1356_REG_BLT_DEST_START_MID SED_REG(0x109)
#define SED1356_REG_BLT_DEST_START_HI SED_REG(0x10a)
#define SED1356_REG_BLT_ADD_OFFSET_LO SED_REG(0x10c)
#define SED1356_REG_BLT_ADD_OFFSET_HI SED_REG(0x10d)
#define SED1356_REG_BLT_WID_LO SED_REG(0x110)
#define SED1356_REG_BLT_WID_HI SED_REG(0x111)
#define SED1356_REG_BLT_HGT_LO SED_REG(0x112)
#define SED1356_REG_BLT_HGT_HI SED_REG(0x113)
#define SED1356_REG_BLT_BG_CLR_LO SED_REG(0x114)
#define SED1356_REG_BLT_BG_CLR_HI SED_REG(0x115)
#define SED1356_REG_BLT_FG_CLR_LO SED_REG(0x118)
#define SED1356_REG_BLT_FG_CLR_HI SED_REG(0x119)
// Look-Up Table Control Registers
#define SED1356_REG_LUT_MODE SED_REG(0x1e0)
#define SED1356_REG_LUT_ADD SED_REG(0x1e2)
#define SED1356_REG_LUT_DATA SED_REG(0x1e4)
// Power and Miscellaneous Control Registers
#define SED1356_REG_PWR_CFG SED_REG(0x1f0)
#define SED1356_REG_PWR_STAT SED_REG(0x1f1)
#define SED1356_REG_WATCHDOG_CTL SED_REG(0x1f4)
#define SED1356_REG_DISP_MODE SED_REG(0x1fc)
// SED1356_REG_REV
#define SED_REV_ID_MASK 0xfc // ID bits - masks off the rev bits
#define SED_REV_ID_1356 BIT4
#define SED_REV_ID_1355 BIT3
// SED1356_REG_GPIO_CFG and SED1356_REG_GPIO_STAT
#define SED1356_GPIO_GPIO3 BIT3 // 0 = input, 1 = output, if configured as GPIO
#define SED1356_GPIO_GPIO2 BIT2
#define SED1356_GPIO_GPIO1 BIT1
// SED1356_REG_MCLK_CFG
#define SED1356_MCLK_DIV2 BIT4
#define SED1356_MCLK_SRC_BCLK BIT0
#define SED1356_MCLK_SRC_CLKI 0x00
// SED1356_REG_LCD_PCLK_CFG, SED1356_REG_CRT_PCLK_CFG
// and SED1356_REG_MEDIA_PCLK_CFG
#define SED1356_PCLK_X2 BIT7 // SED1356_REG_CRT_PCLK_CFG only
#define SED1356_PCLK_DIV1 0x00 << 4
#define SED1356_PCLK_DIV2 0x01 << 4
#define SED1356_PCLK_DIV3 0x02 << 4
#define SED1356_PCLK_DIV4 0x03 << 4
#define SED1356_PCLK_SRC_CLKI 0x00
#define SED1356_PCLK_SRC_BCLK 0x01
#define SED1356_PCLK_SRC_CLKI2 0x02
#define SED1356_PCLK_SRC_MCLK 0x03
// SED1356_REG_MEM_CFG
#define SED1356_MEM_CFG_2CAS_EDO 0x00
#define SED1356_MEM_CFG_2CAS_FPM 0x01
#define SED1356_MEM_CFG_2WE_EDO 0x02
#define SED1356_MEM_CFG_2WE_FPM 0x03
// SED1356_REG_REF_RATE
#define SED1356_REF_TYPE_CBR 0x00 << 6
#define SED1356_REF_TYPE_SELF 0x01 << 6
#define SED1356_REF_TYPE_NONE 0x02 << 6
#define SED1356_REF_RATE_64 0x00 // MCLK / 64
#define SED1356_REF_RATE_128 0x01 // MCLK / 64
#define SED1356_REF_RATE_256 0x02 // MCLK / 64
#define SED1356_REF_RATE_512 0x03 // MCLK / 64
#define SED1356_REF_RATE_1024 0x04 // MCLK / 64
#define SED1356_REF_RATE_2048 0x05 // MCLK / 64
#define SED1356_REF_RATE_4096 0x06 // MCLK / 64
#define SED1356_REF_RATE_8192 0x07 // MCLK / 64
// SED1356_REG_MEM_TMG0
#define SED1356_MEM_TMG0_EDO50_MCLK40 0x01
#define SED1356_MEM_TMG0_EDO50_MCLK33 0x01
#define SED1356_MEM_TMG0_EDO60_MCLK33 0x01
#define SED1356_MEM_TMG0_EDO50_MCLK30 0x12
#define SED1356_MEM_TMG0_EDO60_MCLK30 0x01
#define SED1356_MEM_TMG0_EDO70_MCLK30 0x00
#define SED1356_MEM_TMG0_EDO50_MCLK25 0x12
#define SED1356_MEM_TMG0_EDO60_MCLK25 0x12
#define SED1356_MEM_TMG0_EDO70_MCLK25 0x01
#define SED1356_MEM_TMG0_EDO80_MCLK25 0x00
#define SED1356_MEM_TMG0_EDO50_MCLK20 0x12
#define SED1356_MEM_TMG0_EDO60_MCLK20 0x12
#define SED1356_MEM_TMG0_EDO70_MCLK20 0x12
#define SED1356_MEM_TMG0_EDO80_MCLK20 0x01
#define SED1356_MEM_TMG0_FPM50_MCLK25 0x12
#define SED1356_MEM_TMG0_FPM60_MCLK25 0x01
#define SED1356_MEM_TMG0_FPM50_MCLK20 0x12
#define SED1356_MEM_TMG0_FPM60_MCLK20 0x12
#define SED1356_MEM_TMG0_FPM70_MCLK20 0x11
#define SED1356_MEM_TMG0_FPM80_MCLK20 0x01
// SED1356_REG_MEM_TMG1
#define SED1356_MEM_TMG1_EDO50_MCLK40 0x01
#define SED1356_MEM_TMG1_EDO50_MCLK33 0x01
#define SED1356_MEM_TMG1_EDO60_MCLK33 0x01
#define SED1356_MEM_TMG1_EDO50_MCLK30 0x02
#define SED1356_MEM_TMG1_EDO60_MCLK30 0x01
#define SED1356_MEM_TMG1_EDO70_MCLK30 0x00
#define SED1356_MEM_TMG1_EDO50_MCLK25 0x02
#define SED1356_MEM_TMG1_EDO60_MCLK25 0x02
#define SED1356_MEM_TMG1_EDO70_MCLK25 0x01
#define SED1356_MEM_TMG1_EDO80_MCLK25 0x01
#define SED1356_MEM_TMG1_EDO50_MCLK20 0x02
#define SED1356_MEM_TMG1_EDO60_MCLK20 0x02
#define SED1356_MEM_TMG1_EDO70_MCLK20 0x02
#define SED1356_MEM_TMG1_EDO80_MCLK20 0x01
#define SED1356_MEM_TMG1_FPM50_MCLK25 0x02
#define SED1356_MEM_TMG1_FPM60_MCLK25 0x01
#define SED1356_MEM_TMG1_FPM50_MCLK20 0x02
#define SED1356_MEM_TMG1_FPM60_MCLK20 0x02
#define SED1356_MEM_TMG1_FPM70_MCLK20 0x02
#define SED1356_MEM_TMG1_FPM80_MCLK20 0x01
// Bit definitions
//
// SED1356_REG_PANEL_TYPE
#define SED1356_PANEL_TYPE_EL BIT7
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