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umon bootloader source code, support mips cpu.

FILE flashdev.c:
1,18d0
< /*
<  * %W% %E%
<  *
<  * Copyright (c) 1998-1999 Lucent Technologies, Inc.  All Rights Reserved.
<  *
<  * This software is the confidential and proprietary information of Lucent
<  * Technologies, Inc. ("Confidential Information").  You shall not disclose
<  * such Confidential Information and shall use it only in accordance with
<  * the terms of the license agreement you entered into with Lucent.
<  *
<  * LUCENT TECHNOLOGIES MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
<  * SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
<  * NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
<  * A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.  LUCENT TECHNOLOGIES SHALL
<  * NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING,
<  * MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
<  */
< 
FILE flashpic32.c:
1,18d0
< /*
<  * %W% %E%
<  *
<  * Copyright (c) 1998-1999 Lucent Technologies, Inc.  All Rights Reserved.
<  *
<  * This software is the confidential and proprietary information of Lucent
<  * Technologies, Inc. ("Confidential Information").  You shall not disclose
<  * such Confidential Information and shall use it only in accordance with
<  * the terms of the license agreement you entered into with Lucent.
<  *
<  * LUCENT TECHNOLOGIES MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
<  * SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
<  * NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
<  * A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.  LUCENT TECHNOLOGIES SHALL
<  * NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING,
<  * MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
<  */
< 
20,22c2,4
<    This file contains the 32-bit flash-support code that is relocated to
<    RAM prior to execution.
< */
---
>  * This file contains the 32-bit flash-support code that is relocated to
>  * RAM prior to execution.
>  */
43,45c25,27
<    Based on the 'snum' value, erase the appropriate sector(s).
<    Return 0 if success, else -1.
< */
---
>  * Based on the 'snum' value, erase the appropriate sector(s).
>  * Return 0 if success, else -1.
>  */
60,77c42,46
< 	if ((!FlashProtectWindow) &&
< 	    (fdev->sectors[sector].protected)) {
< 
< 	    add += fdev->sectors[sector].size;
< 	    continue;
< 	}
< 	if ((snum == ALL_SECTORS) || (snum == sector)) {
< 	    register ulong  *lp, *lp1;
< 	    int		    noterased;
< 
< 	    /* See if the sector is already erased: */
< 	    noterased = 0;
< 	    lp = (ulong *)fdev->sectors[sector].begin; 
< 	    lp1 = (ulong *)((char *)lp + fdev->sectors[sector].size); 
< 	    while(lp < lp1) {
< 		if (*lp++ != 0xffffffff) {
< 		    noterased = 1;
< 		    break;
---
> 		if ((!FlashProtectWindow) &&
> 		    (fdev->sectors[sector].protected)) {
> 	
> 		    add += fdev->sectors[sector].size;
> 		    continue;
79,119c48,60
< 	    }
< 	    if (noterased) {
< 		/* Issue the sector erase command sequence: */
< 		Write_aa_to_555();
< 		Write_55_to_2aa();
< 		Write_80_to_555();
< 		Write_aa_to_555();
< 		Write_55_to_2aa();
< 		Write_30_to_(add);
< 
< 		/* Wait for sector erase to complete or timeout.. */
< 		/* DQ7 polling: wait for D7 to be 1. */
< 		/* DQ5 timeout: if DQ7 is 0, and DQ5 = 1, timeout. */
< 		for (;;) {
< 		    val = *(ftype *)add;
< 		    if ((val & 0x00800080) == 0x00800080) {
< 			break;
< 		    }
< 
< 		    /* Check for D5 timeout in upper flash if it's not done */
< 		    if (   (val & 0x00800000) != 0x00800000
< 			&& (val & 0x00200000) != 0          ) {
< 
< 			/* Check D7 once more since D7 and D5 are asynchronous */
< 			val = *(ftype *)add;
< 			if ((val & 0x00800000) != 0x00800000) {
< 			    ret = -1;
< 			    break;
< 			}
< 		    }
< 
< 		    /* Check for D5 timeout in lower flash if it's not done */
< 		    if (   (val & 0x00000080) != 0x00000080
< 			&& (val & 0x00000020) != 0          ) {
< 
< 			/* Check D7 once more since D7 and D5 are asynchronous */
< 			val = *(ftype *)add;
< 			if ((val & 0x00000080) != 0x00000080) {
< 			    ret = -1;
< 			    break;
< 			}
---
> 		if ((snum == ALL_SECTORS) || (snum == sector)) {
> 		    register ulong  *lp, *lp1;
> 		    int		    noterased;
> 	
> 		    /* See if the sector is already erased: */
> 		    noterased = 0;
> 		    lp = (ulong *)fdev->sectors[sector].begin; 
> 		    lp1 = (ulong *)((char *)lp + fdev->sectors[sector].size); 
> 		    while(lp < lp1) {
> 				if (*lp++ != 0xffffffff) {
> 				    noterased = 1;
> 				    break;
> 				}
121,127c62,107
< 
< 		}   /* end wait for complete or timeout */
< 	    }	/* end if not erased */
< 	}   /* end if sector selected for erase */
< 
< 	add += fdev->sectors[sector].size;
< 
---
> 		    if (noterased) {
> 				/* Issue the sector erase command sequence: */
> 				Write_aa_to_555();
> 				Write_55_to_2aa();
> 				Write_80_to_555();
> 				Write_aa_to_555();
> 				Write_55_to_2aa();
> 				Write_30_to_(add);
> 		
> 				/* Wait for sector erase to complete or timeout.. */
> 				/* DQ7 polling: wait for D7 to be 1. */
> 				/* DQ5 timeout: if DQ7 is 0, and DQ5 = 1, timeout. */
> 				for (;;) {
> 				    val = *(ftype *)add;
> 				    if ((val & 0x00800080) == 0x00800080) {
> 						break;
> 				    }
> 	
> 				    /* Check for D5 timeout in upper flash if it's not done */
> 				    if (((val & 0x00800000) != 0x00800000) &&
> 						((val & 0x00200000) != 0)) {
> 		
> 						/* Check D7 again since D7 and D5 are asynchronous */
> 						val = *(ftype *)add;
> 						if ((val & 0x00800000) != 0x00800000) {
> 						    ret = -1;
> 						    break;
> 						}
> 				    }
> 	
> 				    /* Check for D5 timeout in lower flash if it's not done */
> 				    if (((val & 0x00000080) != 0x00000080) &&
> 						((val & 0x00000020) != 0)) {
> 		
> 						/* Check D7 again since D7 and D5 are asynchronous */
> 						val = *(ftype *)add;
> 						if ((val & 0x00000080) != 0x00000080) {
> 						    ret = -1;
> 						    break;
> 						}
> 				    }
> 		
> 				}   /* end wait for complete or timeout */
> 		    }	/* end if not erased */
> 		}   /* end if sector selected for erase */
> 		add += fdev->sectors[sector].size;
133,134c113,114
< 	Write_f0_to_555();
< 	val = Read_555();
---
> 		Write_f0_to_555();
> 		val = Read_555();
140,142c120,122
<    Function place holder to determine the "end" of the
<    sectorerase() function.
< */
---
>  * Function place holder to determine the "end" of the
>  * sectorerase() function.
>  */
154,155c134,135
<    Return 0 if successful, else -1.
< */
---
>  * Return 0 if successful, else -1.
>  */
159c139,140
< uchar	*src, *dest;
---
> uchar	*src;
> register uchar *dest;
163c144
<     ftype		tmp, d7test;
---
>     register ftype		tmp, d7test;
171,196c152
<     while (timeout == 0 && cnt > 0) {
< 	/* First fill the aligned source buffer from the source.  If the   */
< 	/* destination is not 4-byte aligned, also grab bytes from the     */
< 	/* flash prior to the destination to allow all 32 bits to be       */
< 	/* written at once.  If the source length is too short to fill all */
< 	/* 4 bytes, grab bytes from the flash following the destination to */
< 	/* allow all 32 bits to be written at once.                        */
< 	bidx = 0;
< 	while (prefetch) {
< 	    asrc.buf[bidx] = dest[bidx];
< 	    bidx++;
< 	    prefetch--;
< 	}
< 	while (bidx < 4) {
< 	    if (cnt > 0) {
< 		asrc.buf[bidx] = *src++;
< 		cnt--;
< 	    } else {
< 		asrc.buf[bidx] = dest[bidx];
< 	    }
< 	    bidx++;
< 	}
< 
< 	/* Now asrc.val has the 4-bytes to write to the flash. */
< 
< 	/* Flash write command */
---
> 	/* Unlock Bypass Command: */
199c155
< 	Write_a0_to_555();
---
> 	Write_20_to_555();
201,221c157,169
< 	/* Write the value */
< 	Fwrite(dest, &asrc.val);
< 	d7test = asrc.val & 0x00800080;
< 
< 	/* Wait for flash write to complete (each device might complete */
< 	/* at a different time).                                        */
< 	for (;;) {
< 	    tmp = *(ftype *)dest;
< 	    if ((tmp & 0x00800080) == d7test) {
< 		break;
< 	    }
< 
< 	    /* Check for D5 timeout in upper flash if it's not done */
< 	    if (   (tmp & 0x00800000) != (d7test & 0x00800000)
< 		&& (tmp & 0x00200000) != 0                     ) {
< 
< 		/* Check D7 once more since D7 and D5 are asynchronous */
< 		tmp = *(ftype *)dest;
< 		if ((tmp & 0x00800000) != (d7test & 0x00800000)) {
< 		    timeout = -1;
< 		    break;
---
>     while (timeout == 0 && cnt > 0) {
> 		/* First fill the aligned source buffer from the source.  If the
> 		 * destination is not 4-byte aligned, also grab bytes from the
> 		 * flash prior to the destination to allow all 32 bits to be
> 		 * written at once.  If the source length is too short to fill all
> 		 * 4 bytes, grab bytes from the flash following the destination to
> 		 * allow all 32 bits to be written at once.
> 		 */
> 		bidx = 0;
> 		while (prefetch) {
> 		    asrc.buf[bidx] = dest[bidx];
> 		    bidx++;
> 		    prefetch--;
223,233c171,222
< 	    }
< 
< 	    /* Check for D5 timeout in lower flash if it's not done */
< 	    if (   (tmp & 0x00000080) != (d7test & 0x00000080)
< 		&& (tmp & 0x00000020) != 0                     ) {
< 
< 		/* Check D7 once more since D7 and D5 are asynchronous */
< 		tmp = *(ftype *)dest;
< 		if ((tmp & 0x00000080) != (d7test & 0x00000080)) {
< 		    timeout = -1;
< 		    break;
---
> 		while (bidx < 4) {
> 		    if (cnt > 0) {
> 				asrc.buf[bidx] = *src++;
> 				cnt--;
> 		    }
> 			else {
> 				asrc.buf[bidx] = dest[bidx];
> 		    }
> 		    bidx++;
> 		}
> 	
> 		/* Now asrc.val has the 4-bytes to write to the flash. */
> 	
> 		/* Bypass Program command */
> 		Write_a0_to_555();
> 	
> 		/* Write the value */
> 		Fwrite(dest, &asrc.val);
> 		d7test = asrc.val & 0x00800080;
> 	
> 		/* Wait for flash write to complete (each device might complete
> 		 * at a different time).
> 		 */
> 		for (;;) {
> 		    tmp = *(ftype *)dest;
> 		    if ((tmp & 0x00800080) == d7test) {
> 				break;
> 		    }
> 	
> 		    /* Check for D5 timeout in upper flash if it's not done */
> 		    if ((tmp & 0x00800000) != (d7test & 0x00800000) &&
> 				(tmp & 0x00200000) != 0) {
> 	
> 				/* Check D7 once more since D7 and D5 are asynchronous */
> 				tmp = *(ftype *)dest;
> 				if ((tmp & 0x00800000) != (d7test & 0x00800000)) {
> 				    timeout = -1;
> 				    break;
> 				}
> 		    }
> 	
> 		    /* Check for D5 timeout in lower flash if it's not done */
> 		    if ((tmp & 0x00000080) != (d7test & 0x00000080) &&
> 				(tmp & 0x00000020) != 0) {
> 	
> 				/* Check D7 once more since D7 and D5 are asynchronous */
> 				tmp = *(ftype *)dest;
> 				if ((tmp & 0x00000080) != (d7test & 0x00000080)) {
> 				    timeout = -1;