risc.h

umon bootloader source code, support mips cpu.

/*
*********************************************************************************************************
*                                Copyright (c) 2005 vBridge Microsystem, Inc.  
*                                      Unpublished & Not for Publication
*                                            All Rights Reserved                   
*   
* File:                      
*                                                                         
* Description : Revised from zhong xiang's mips_4kec_regs.h   
*             
* Date:         Dec 16, 2005                                                           
**********************************************************************************************************
*/


#ifndef __RISC_H__
#define __RISC_H__


#define TRUE 	1
#define FALSE	0

#define SUCCESSFUL 1
#define FAILURE	0
#define FAILED	0

#define V_BASE_ADDR	0xa0000000

/* Global space address: SDRAM/queue/stream */
#define GLOBAL_B_ADDR 0x00000000
#define GLOBAL_E_ADDR 0x0fffffff

/* boot space address */
#define BOOT_B_ADDR 0x1fc00000
#define BOOT_E_ADDR 0x1fffffff

/* Internal SPRAM address: 2Mbyte */
#define I_SPRAM_B_ADDR 0x1f800000
#define I_SPRAM_E_ADDR 0x1f9fffff

/* External SPRAM address: 2Mbyte */
#define E_SPRAM_B_ADDR 0x1fa00000
#define E_SPRAM_E_ADDR 0x1fbfffff


/* Global space */
/* The SDRAM: 64Mbytes */
#define SDRAM_B_ADDR 0x00000000
#define SDRAM_E_ADDR 0x03ffffff

/* The SDRAM queues
* bit[15:8] : queue ID 
* bit[19:16]: extended video stream context ID, bit16=1 for UV, bit16=0 for Y
*/
#define QUEUE_B_ADDR 0x04000000
#define QUEUE_E_ADDR 0x07ffffff

/* The on chip registers 
* bit[20:16]:block ID
* bit[15:0] :local register address of each block
*/
#define REGS_B_ADDR 0x08000000
#define REGS_E_ADDR 0x0bffffff

/* The streams
* bit[15: 8]: stream ID
* bit[19:16]: steam operation code */
#define STREAM_B_ADDR 0x0c000000
#define STREAM_E_ADDR 0x0fffffff

//Block ID
#define RISC_BLOCK	0x0
#define CCTL_BLOCK 	0x1
#define MC_BLOCK 	0x2
#define SIF_BLOCK 	0x3
#define SC_BLOCK	0x4
#define VIN_BLOCK	0x5
#define VOUT_BLOCK	0x6
#define AUD_BLOCK	0x7
#define DMAC_BLOCK	0x8
#define PPE_BLOCK	0x9
#define PIF_BLOCK	0xA
#define VSC_BLOCK	0xB
#define EMAC0_BLOCK	0xC
#define EMAC1_BLOCK	0xD
#define SEC_BLOCK	0xE
#define UART_BLOCK	0xF

#define BLOCK_BASE_ADDR(BLOCK_ID) (V_BASE_ADDR + REGS_B_ADDR + (BLOCK_ID<<16))

// RISC local register specifications 
#define RISC0_CTL 	0x0
#define RISC1_CTL 	0x4
#define RISC_COM_CTL 	0x8
#define RISC_PCNT	0xC
#define RISC_INT_STATUS 0x10
#define RISC_VCNT	0x14
#define RISC_VCNT_VAL	0x18
#define RISC_SEMAPHORE0 0x20
#define RISC_SEMAPHORE1 0x24
#define RISC_SEMAPHORE2 0x28
#define RISC_SEMAPHORE3 0x2C
#define RISC_SEMAPHORE4 0x30
#define RISC_SEMAPHORE5 0x34
#define RISC_SEMAPHORE6 0x38
#define RISC_SEMAPHORE7 0x3C
#define RISC_CNT0	0x40
#define RISC_CNT1	0x44
#define RISC_CNT2	0x48
#define RISC_CNT3	0x4C
#define RISC_CNT4	0x50
#define RISC_CNT5	0x54
#define RISC_CNT6	0x58
#define RISC_CNT7 	0x5C
#define RISC_CRC_VAL	0x60
#define RISC_CRC10_DATA	0x64
#define RISC_CRC16_DATA 0x68
#define RISC_CRC32_DATA 0x6C
#define RISC_CRC_CTL	0x70
#define RISC_GPIO	0x80
#define RISC_GPIO_DIR	0x84

#define RISC_REGS_ADDR(REGS)	(BLOCK_BASE_ADDR(RISC_BLOCK) + REGS)

#define RISC_SPRAM_B_ADDR 0x3000
#define RISC_SPRAM_E_ADDR 0x7ffc




#endif // __RISC_H__