tb_div2_01.v

来自「32位除法器的测试程序」· Verilog 代码 · 共 52 行

`timescale 100ps/100ps

module top;

parameter n=32;    
parameter m=16;
parameter clock_cycle=10;

  reg clock;
  reg start;
  reg [n-1:0]    dividend;
  reg [n-1:0]    divisor;
  
  wire finish;
  wire error;
  wire [n+m-1:0]  quotient;
  wire [n-1:0]    remainder;
  

always #clock_cycle clock=~clock;
initial
  begin
    clock=0;
    start=0;
    #1    //dividend=32'b00000000000011100000000000000000;
           //divisor=32'b00000000000000110000000000000000;
          dividend=32'b10010010010011100000000000000000;
           divisor=32'b00000010010000110000000000000000;
          //dividend=32'b00011100000000000000000000000000;
           //divisor=32'b00000000000000110000000000000000;

         //dividend = 32'b01111101011011011111010111111010;
         //divisor  = 32'b11111001001001111001010011110010;
          
    #10 start=1;
      
    #1100 $stop;
  end
  
  div2 m1(               
       .dividend(dividend),         
       .divisor(divisor),           
       .quotient(quotient),          
       .remainder(remainder),        
       .start(start),              
       .clock(clock),              
       .finish(finish),             
       .error(error));    
       
endmodule