dsp28_mcbsp.c

TMS320F2812DSP与DAC7731的接口程序

//
//      TMDX ALPHA RELEASE
//      Intended for product evaluation purposes
//
//###########################################################################
//
// FILE:	DSP28_McBSP.c
//
// TITLE:	DSP28 Deviec McBSP Initialization & Support Functions.
//
//###########################################################################
//
//  Ver | dd mmm yyyy | Who  | Description of changes
// =====|=============|======|===============================================
//  0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
//  0.56| 20 May 2002 | L.H. | No change
//  0.57| 27 May 2002 | L.H. | No change
//###########################################################################

#include "DSP28_Device.h"

//---------------------------------------------------------------------------
// InitMcbsp: 
//---------------------------------------------------------------------------
// This function initializes the McBSP to a known state.
//
void InitMcbsp(void)
{
	EALLOW;
	GpioMuxRegs.GPFMUX.all = 0x3F00;
	GpioMuxRegs.GPFDIR.bit.GPIOF14 = 1; //out
	
	EDIS;

    	
	PieCtrl.PIEIER6.bit.INTx5 = 1;	//McBSP MRINT
	PieCtrl.PIEIER6.bit.INTx6 = 1;	//McBSP MXINT	10 PRI
	
	McbspRegs.SPCR1.bit.RRST = 0;
	//The serial port receiver/transmitter is disabled and in reset state.
	McbspRegs.SPCR2.bit.XRST = 0;	
	//The serial port transmitter is disabled and in reset state.
	McbspRegs.SPCR2.bit.GRST = 0;	
	//Sample rate generator is reset.	
	McbspRegs.SPCR1.all = 0;
	
	McbspRegs.XCR1.all = 0x40;
	McbspRegs.XCR2.all = 0x01;
	McbspRegs.RCR1.all = 0x40;	//Receive word length 1 010b 16 bits
	McbspRegs.RCR2.all = 0x01;	//Receive data delay 01b 1-bit data delay
	//Receive frame length 1  00b 1 word per frame	
	//Receive phases Single phase frame
	//Receive frame length   00b 1 word per frame
	//Receive word length 000b 8 bits	
	//00b No companding, data transfer starts with MSB first.
	McbspRegs.PCR1.all = 0x0A00;
	
	McbspRegs.SPCR2.bit.GRST = 1;
	
	McbspRegs.SPCR1.bit.RINTM=0;
	McbspRegs.SPCR2.bit.XINTM=0;	
	NOP;
	NOP;
	
	//Sample Rate Generator Registers
	McbspRegs.SRGR1.all = 0xffff;
	//Frame width.  Sample rate generator clock divider
	McbspRegs.SRGR2.all = 0x2000;
	//0 The sample rate generator clock (CLKG) is free running.
	//0 1 LSPCLK - Internal clock	
	//Transmit frame sync signal (FSX) due to DXR(1/2)-to-XSR(1/2) copy.
//-----------------McBSP as the SPI Master------------------------
	McbspRegs.SPCR1.bit.CLKSTP=0x2;		//The clock stop mode
	McbspRegs.PCR1.all = 0x0A08;
//----------------------------------------------------------------
//	McbspRegs.SPCR1.bit.DLB = 1;	// enabled Digital loop back mode		
	McbspRegs.SPCR1.bit.RRST = 1;	// enabled	
	McbspRegs.SPCR2.bit.XRST = 1;	// enabled
	
	
	
	NOP;
	NOP;
}

unsigned int Mcbsp_TxRdy(void)
{
	if(McbspRegs.SPCR2.bit.XRDY == 1)
	{
		return(1);
	}
	else
	{
		return(0);
	}
}

unsigned int Mcbsp_RxRdy(void)
{
	if(McbspRegs.SPCR1.bit.RRDY == 1)
	{
		return(1);
	}
	else
	{
		return(0);
	}
}
	
//===========================================================================
// No more.
//===========================================================================