📄 schk.vhd.bak
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LIBRARY IEEE;
use ieee.std_logic_1164.all;
entity SCHK IS
PORT(DIN,CLK,CLR:IN STD_LOGIC;
AB:OUT STD_LOGIC);
END ENTITY SCHK;
ARCHITECTURE behav of SCHK IS
SIGNAL Q : INTEGER RANGE 0 TO 5;
SIGNAL D : STD_LOGIC_VECTOR(4 DOWNTO 0);
begin
D <= "11010" ;
PROCESS(CLK,CLR)
BEGIN
IF CLR='1' THEN Q <= 0;
ELSIF CLK'EVENT AND CLK='1' THEN
CASE Q IS
WHEN 0=> IF DIN=D(4) THEN Q<=1;ELSE Q<=0;END IF;
WHEN 1=> IF DIN=D(3) THEN Q<=2;ELSE Q<=0;END IF;
WHEN 2=> IF DIN=D(2) THEN Q<=3;ELSE Q<=0;END IF;
WHEN 3=> IF DIN=D(1) THEN Q<=4;ELSE Q<=0;END IF;
WHEN 4=> IF DIN=D(0) THEN Q<=5;ELSE Q<=0;END IF;
WHEN OTHERS => Q <= 0;
END CASE;
END IF;
END PROCESS;
process(Q)
BEGIN
IF Q=5 THEN AB <= '1' ;
ELSE AB <= '0' ;
END IF;
END PROCESS;
END BEHAV;
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