schk.tan.rpt

用状态机实现串行序列检测器的设计 若检测到串行序列11010则输出为1 否则输出为0 并对其进行仿真和硬件测试

; Slack ; Required tsu ; Actual tsu ; From ; To   ; To Clock ;
+-------+--------------+------------+------+------+----------+
; N/A   ; None         ; 1.500 ns   ; DIN  ; Q[2] ; CLK      ;
; N/A   ; None         ; 1.300 ns   ; DIN  ; Q[0] ; CLK      ;
; N/A   ; None         ; 1.300 ns   ; DIN  ; Q[1] ; CLK      ;
+-------+--------------+------------+------+------+----------+


+------------------------------------------------------------+
; tco                                                        ;
+-------+--------------+------------+------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------+----+------------+
; N/A   ; None         ; 15.100 ns  ; Q[0] ; AB ; CLK        ;
; N/A   ; None         ; 15.000 ns  ; Q[2] ; AB ; CLK        ;
; N/A   ; None         ; 14.900 ns  ; Q[1] ; AB ; CLK        ;
+-------+--------------+------------+------+----+------------+


+------------------------------------------------------------------+
; th                                                               ;
+---------------+-------------+-----------+------+------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To   ; To Clock ;
+---------------+-------------+-----------+------+------+----------+
; N/A           ; None        ; 0.000 ns  ; DIN  ; Q[0] ; CLK      ;
; N/A           ; None        ; 0.000 ns  ; DIN  ; Q[1] ; CLK      ;
; N/A           ; None        ; -0.200 ns ; DIN  ; Q[2] ; CLK      ;
+---------------+-------------+-----------+------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
    Info: Processing started: Tue Nov 27 21:14:19 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off SCHK -c SCHK
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 250.0 MHz between source register "Q[2]" and destination register "Q[0]"
    Info: fmax restricted to Clock High delay (2.0 ns) plus Clock Low delay (2.0 ns) : restricted to 4.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.100 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_E49; Fanout = 4; REG Node = 'Q[2]'
            Info: 2: + IC(0.100 ns) + CELL(1.000 ns) = 1.100 ns; Loc. = LC1_E49; Fanout = 4; REG Node = 'Q[0]'
            Info: Total cell delay = 1.000 ns ( 90.91 % )
            Info: Total interconnect delay = 0.100 ns ( 9.09 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 5.600 ns
                Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_53; Fanout = 3; CLK Node = 'CLK'
                Info: 2: + IC(3.600 ns) + CELL(0.000 ns) = 5.600 ns; Loc. = LC1_E49; Fanout = 4; REG Node = 'Q[0]'
                Info: Total cell delay = 2.000 ns ( 35.71 % )
                Info: Total interconnect delay = 3.600 ns ( 64.29 % )
            Info: - Longest clock path from clock "CLK" to source register is 5.600 ns
                Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_53; Fanout = 3; CLK Node = 'CLK'
                Info: 2: + IC(3.600 ns) + CELL(0.000 ns) = 5.600 ns; Loc. = LC2_E49; Fanout = 4; REG Node = 'Q[2]'
                Info: Total cell delay = 2.000 ns ( 35.71 % )
                Info: Total interconnect delay = 3.600 ns ( 64.29 % )
        Info: + Micro clock to output delay of source is 0.800 ns
        Info: + Micro setup delay of destination is 0.600 ns
Info: tsu for register "Q[2]" (data pin = "DIN", clock pin = "CLK") is 1.500 ns
    Info: + Longest pin to register delay is 6.500 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 3; PIN Node = 'DIN'
        Info: 2: + IC(3.500 ns) + CELL(1.000 ns) = 6.500 ns; Loc. = LC2_E49; Fanout = 4; REG Node = 'Q[2]'
        Info: Total cell delay = 3.000 ns ( 46.15 % )
        Info: Total interconnect delay = 3.500 ns ( 53.85 % )
    Info: + Micro setup delay of destination is 0.600 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 5.600 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_53; Fanout = 3; CLK Node = 'CLK'
        Info: 2: + IC(3.600 ns) + CELL(0.000 ns) = 5.600 ns; Loc. = LC2_E49; Fanout = 4; REG Node = 'Q[2]'
        Info: Total cell delay = 2.000 ns ( 35.71 % )
        Info: Total interconnect delay = 3.600 ns ( 64.29 % )
Info: tco from clock "CLK" to destination pin "AB" through register "Q[0]" is 15.100 ns
    Info: + Longest clock path from clock "CLK" to source register is 5.600 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_53; Fanout = 3; CLK Node = 'CLK'
        Info: 2: + IC(3.600 ns) + CELL(0.000 ns) = 5.600 ns; Loc. = LC1_E49; Fanout = 4; REG Node = 'Q[0]'
        Info: Total cell delay = 2.000 ns ( 35.71 % )
        Info: Total interconnect delay = 3.600 ns ( 64.29 % )
    Info: + Micro clock to output delay of source is 0.800 ns
    Info: + Longest register to pin delay is 8.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E49; Fanout = 4; REG Node = 'Q[0]'
        Info: 2: + IC(0.100 ns) + CELL(1.400 ns) = 1.500 ns; Loc. = LC4_E49; Fanout = 1; COMB Node = 'Equal0~12'
        Info: 3: + IC(1.000 ns) + CELL(6.200 ns) = 8.700 ns; Loc. = PIN_206; Fanout = 0; PIN Node = 'AB'
        Info: Total cell delay = 7.600 ns ( 87.36 % )
        Info: Total interconnect delay = 1.100 ns ( 12.64 % )
Info: th for register "Q[0]" (data pin = "DIN", clock pin = "CLK") is 0.000 ns
    Info: + Longest clock path from clock "CLK" to destination register is 5.600 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_53; Fanout = 3; CLK Node = 'CLK'
        Info: 2: + IC(3.600 ns) + CELL(0.000 ns) = 5.600 ns; Loc. = LC1_E49; Fanout = 4; REG Node = 'Q[0]'
        Info: Total cell delay = 2.000 ns ( 35.71 % )
        Info: Total interconnect delay = 3.600 ns ( 64.29 % )
    Info: + Micro hold delay of destination is 0.700 ns
    Info: - Shortest pin to register delay is 6.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 3; PIN Node = 'DIN'
        Info: 2: + IC(3.500 ns) + CELL(0.800 ns) = 6.300 ns; Loc. = LC1_E49; Fanout = 4; REG Node = 'Q[0]'
        Info: Total cell delay = 2.800 ns ( 44.44 % )
        Info: Total interconnect delay = 3.500 ns ( 55.56 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 114 megabytes of memory during processing
    Info: Processing ended: Tue Nov 27 21:14:21 2007
    Info: Elapsed time: 00:00:02