prev_cmp_jtdkz.tan.qmsg

一条主干道

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK CNT1\[3\] lpm_counter:CNT1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 10.900 ns register " "Info: tco from clock \"CLK\" to destination pin \"CNT1\[3\]\" through register \"lpm_counter:CNT1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]\" is 10.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.400 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 1.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 0.400 ns CLK 1 CLK PIN_79 29 " "Info: 1: + IC(0.000 ns) + CELL(0.400 ns) = 0.400 ns; Loc. = PIN_79; Fanout = 29; CLK Node = 'CLK'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.000 ns) 1.400 ns lpm_counter:CNT1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC4_E35 3 " "Info: 2: + IC(1.000 ns) + CELL(0.000 ns) = 1.400 ns; Loc. = LC4_E35; Fanout = 3; REG Node = 'lpm_counter:CNT1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { CLK lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.400 ns ( 28.57 % ) " "Info: Total cell delay = 0.400 ns ( 28.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 71.43 % ) " "Info: Total interconnect delay = 1.000 ns ( 71.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.400 ns" { CLK CLK~out lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.400ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.800 ns + " "Info: + Micro clock to output delay of source is 0.800 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.700 ns + Longest register pin " "Info: + Longest register to pin delay is 8.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:CNT1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 1 REG LC4_E35 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_E35; Fanout = 3; REG Node = 'lpm_counter:CNT1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(6.200 ns) 8.700 ns CNT1\[3\] 2 PIN PIN_144 0 " "Info: 2: + IC(2.500 ns) + CELL(6.200 ns) = 8.700 ns; Loc. = PIN_144; Fanout = 0; PIN Node = 'CNT1\[3\]'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "8.700 ns" { lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] CNT1[3] } "NODE_NAME" } } { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.200 ns ( 71.26 % ) " "Info: Total cell delay = 6.200 ns ( 71.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 28.74 % ) " "Info: Total interconnect delay = 2.500 ns ( 28.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "8.700 ns" { lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] CNT1[3] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "8.700 ns" { lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] CNT1[3] } { 0.000ns 2.500ns } { 0.000ns 6.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.400 ns" { CLK CLK~out lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.400ns 0.000ns } "" } } { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "8.700 ns" { lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] CNT1[3] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "8.700 ns" { lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] CNT1[3] } { 0.000ns 2.500ns } { 0.000ns 6.200ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "EN S CLK -0.900 ns register " "Info: th for register \"EN\" (data pin = \"S\", clock pin = \"CLK\") is -0.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.400 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 1.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 0.400 ns CLK 1 CLK PIN_79 29 " "Info: 1: + IC(0.000 ns) + CELL(0.400 ns) = 0.400 ns; Loc. = PIN_79; Fanout = 29; CLK Node = 'CLK'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.000 ns) 1.400 ns EN 2 REG LC8_E33 6 " "Info: 2: + IC(1.000 ns) + CELL(0.000 ns) = 1.400 ns; Loc. = LC8_E33; Fanout = 6; REG Node = 'EN'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { CLK EN } "NODE_NAME" } } { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.400 ns ( 28.57 % ) " "Info: Total cell delay = 0.400 ns ( 28.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 71.43 % ) " "Info: Total interconnect delay = 1.000 ns ( 71.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK EN } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.400 ns" { CLK CLK~out EN } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.400ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.700 ns + " "Info: + Micro hold delay of destination is 0.700 ns" {  } { { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 0.400 ns S 1 PIN PIN_184 9 " "Info: 1: + IC(0.000 ns) + CELL(0.400 ns) = 0.400 ns; Loc. = PIN_184; Fanout = 9; PIN Node = 'S'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { S } "NODE_NAME" } } { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(0.700 ns) 3.000 ns EN 2 REG LC8_E33 6 " "Info: 2: + IC(1.900 ns) + CELL(0.700 ns) = 3.000 ns; Loc. = LC8_E33; Fanout = 6; REG Node = 'EN'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.600 ns" { S EN } "NODE_NAME" } } { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.100 ns ( 36.67 % ) " "Info: Total cell delay = 1.100 ns ( 36.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns ( 63.33 % ) " "Info: Total interconnect delay = 1.900 ns ( 63.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { S EN } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { S S~out EN } { 0.000ns 0.000ns 1.900ns } { 0.000ns 0.400ns 0.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK EN } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.400 ns" { CLK CLK~out EN } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.400ns 0.000ns } "" } } { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { S EN } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { S S~out EN } { 0.000ns 0.000ns 1.900ns } { 0.000ns 0.400ns 0.700ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 29 22:05:37 2007 " "Info: Processing ended: Thu Nov 29 22:05:37 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}