jtdkz.tan.qmsg

一条主干道

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 5 -1 0 } } { "d:/quartus7.1/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.1/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register lpm_counter:CNT1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] register M0\[2\] 51.55 MHz 19.4 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 51.55 MHz between source register \"lpm_counter:CNT1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]\" and destination register \"M0\[2\]\" (period= 19.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.300 ns + Longest register register " "Info: + Longest register to register delay is 8.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:CNT1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 1 REG LC7_D25 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_D25; Fanout = 3; REG Node = 'lpm_counter:CNT1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.500 ns) 1.600 ns LessThan0~34 2 COMB LC1_D25 7 " "Info: 2: + IC(0.100 ns) + CELL(1.500 ns) = 1.600 ns; Loc. = LC1_D25; Fanout = 7; COMB Node = 'LessThan0~34'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] LessThan0~34 } "NODE_NAME" } } { "d:/quartus7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1657 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.400 ns) 3.900 ns p2~1 3 COMB LC2_D19 10 " "Info: 3: + IC(0.900 ns) + CELL(1.400 ns) = 3.900 ns; Loc. = LC2_D19; Fanout = 10; COMB Node = 'p2~1'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { LessThan0~34 p2~1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.400 ns) 5.400 ns Selector5~164 4 COMB LC1_D19 2 " "Info: 4: + IC(0.100 ns) + CELL(1.400 ns) = 5.400 ns; Loc. = LC1_D19; Fanout = 2; COMB Node = 'Selector5~164'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { p2~1 Selector5~164 } "NODE_NAME" } } { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(1.300 ns) 7.500 ns Selector2~252 5 COMB LC4_D18 1 " "Info: 5: + IC(0.800 ns) + CELL(1.300 ns) = 7.500 ns; Loc. = LC4_D18; Fanout = 1; COMB Node = 'Selector2~252'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { Selector5~164 Selector2~252 } "NODE_NAME" } } { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.700 ns) 8.300 ns M0\[2\] 6 REG LC6_D18 2 " "Info: 6: + IC(0.100 ns) + CELL(0.700 ns) = 8.300 ns; Loc. = LC6_D18; Fanout = 2; REG Node = 'M0\[2\]'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { Selector2~252 M0[2] } "NODE_NAME" } } { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns ( 75.90 % ) " "Info: Total cell delay = 6.300 ns ( 75.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 24.10 % ) " "Info: Total interconnect delay = 2.000 ns ( 24.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "8.300 ns" { lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] LessThan0~34 p2~1 Selector5~164 Selector2~252 M0[2] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "8.300 ns" { lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] LessThan0~34 p2~1 Selector5~164 Selector2~252 M0[2] } { 0.000ns 0.100ns 0.900ns 0.100ns 0.800ns 0.100ns } { 0.000ns 1.500ns 1.400ns 1.400ns 1.300ns 0.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.400 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 1.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 0.400 ns CLK 1 CLK PIN_79 29 " "Info: 1: + IC(0.000 ns) + CELL(0.400 ns) = 0.400 ns; Loc. = PIN_79; Fanout = 29; CLK Node = 'CLK'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.000 ns) 1.400 ns M0\[2\] 2 REG LC6_D18 2 " "Info: 2: + IC(1.000 ns) + CELL(0.000 ns) = 1.400 ns; Loc. = LC6_D18; Fanout = 2; REG Node = 'M0\[2\]'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { CLK M0[2] } "NODE_NAME" } } { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.400 ns ( 28.57 % ) " "Info: Total cell delay = 0.400 ns ( 28.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 71.43 % ) " "Info: Total interconnect delay = 1.000 ns ( 71.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK M0[2] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.400 ns" { CLK CLK~out M0[2] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.400ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.400 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 1.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 0.400 ns CLK 1 CLK PIN_79 29 " "Info: 1: + IC(0.000 ns) + CELL(0.400 ns) = 0.400 ns; Loc. = PIN_79; Fanout = 29; CLK Node = 'CLK'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.000 ns) 1.400 ns lpm_counter:CNT1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC7_D25 3 " "Info: 2: + IC(1.000 ns) + CELL(0.000 ns) = 1.400 ns; Loc. = LC7_D25; Fanout = 3; REG Node = 'lpm_counter:CNT1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { CLK lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.400 ns ( 28.57 % ) " "Info: Total cell delay = 0.400 ns ( 28.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 71.43 % ) " "Info: Total interconnect delay = 1.000 ns ( 71.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.400 ns" { CLK CLK~out lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.400ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK M0[2] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.400 ns" { CLK CLK~out M0[2] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.400ns 0.000ns } "" } } { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.400 ns" { CLK CLK~out lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.400ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.800 ns + " "Info: + Micro clock to output delay of source is 0.800 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 45 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } } { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 45 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "8.300 ns" { lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] LessThan0~34 p2~1 Selector5~164 Selector2~252 M0[2] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "8.300 ns" { lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] LessThan0~34 p2~1 Selector5~164 Selector2~252 M0[2] } { 0.000ns 0.100ns 0.900ns 0.100ns 0.800ns 0.100ns } { 0.000ns 1.500ns 1.400ns 1.400ns 1.300ns 0.700ns } "" } } { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK M0[2] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.400 ns" { CLK CLK~out M0[2] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.400ns 0.000ns } "" } } { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.400 ns" { CLK CLK~out lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.400ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "M0\[2\] S CLK 10.600 ns register " "Info: tsu for register \"M0\[2\]\" (data pin = \"S\", clock pin = \"CLK\") is 10.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.400 ns + Longest pin register " "Info: + Longest pin to register delay is 11.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns S 1 PIN PIN_53 9 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_53; Fanout = 9; PIN Node = 'S'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { S } "NODE_NAME" } } { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.900 ns) + CELL(1.200 ns) 8.100 ns Selector10~69 2 COMB LC7_D18 2 " "Info: 2: + IC(4.900 ns) + CELL(1.200 ns) = 8.100 ns; Loc. = LC7_D18; Fanout = 2; COMB Node = 'Selector10~69'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { S Selector10~69 } "NODE_NAME" } } { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.000 ns) 9.200 ns Selector2~255 3 COMB LC3_D18 1 " "Info: 3: + IC(0.100 ns) + CELL(1.000 ns) = 9.200 ns; Loc. = LC3_D18; Fanout = 1; COMB Node = 'Selector2~255'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.100 ns" { Selector10~69 Selector2~255 } "NODE_NAME" } } { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 10.600 ns Selector2~252 4 COMB LC4_D18 1 " "Info: 4: + IC(0.000 ns) + CELL(1.400 ns) = 10.600 ns; Loc. = LC4_D18; Fanout = 1; COMB Node = 'Selector2~252'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { Selector2~255 Selector2~252 } "NODE_NAME" } } { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.700 ns) 11.400 ns M0\[2\] 5 REG LC6_D18 2 " "Info: 5: + IC(0.100 ns) + CELL(0.700 ns) = 11.400 ns; Loc. = LC6_D18; Fanout = 2; REG Node = 'M0\[2\]'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { Selector2~252 M0[2] } "NODE_NAME" } } { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns ( 55.26 % ) " "Info: Total cell delay = 6.300 ns ( 55.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.100 ns ( 44.74 % ) " "Info: Total interconnect delay = 5.100 ns ( 44.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "11.400 ns" { S Selector10~69 Selector2~255 Selector2~252 M0[2] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "11.400 ns" { S S~out Selector10~69 Selector2~255 Selector2~252 M0[2] } { 0.000ns 0.000ns 4.900ns 0.100ns 0.000ns 0.100ns } { 0.000ns 2.000ns 1.200ns 1.000ns 1.400ns 0.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 45 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.400 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 1.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 0.400 ns CLK 1 CLK PIN_79 29 " "Info: 1: + IC(0.000 ns) + CELL(0.400 ns) = 0.400 ns; Loc. = PIN_79; Fanout = 29; CLK Node = 'CLK'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.000 ns) 1.400 ns M0\[2\] 2 REG LC6_D18 2 " "Info: 2: + IC(1.000 ns) + CELL(0.000 ns) = 1.400 ns; Loc. = LC6_D18; Fanout = 2; REG Node = 'M0\[2\]'" {  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { CLK M0[2] } "NODE_NAME" } } { "JTDKZ.vhd" "" { Text "D:/EDA/traffic/JTDKZ.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.400 ns ( 28.57 % ) " "Info: Total cell delay = 0.400 ns ( 28.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 71.43 % ) " "Info: Total interconnect delay = 1.000 ns ( 71.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK M0[2] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.400 ns" { CLK CLK~out M0[2] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.400ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "11.400 ns" { S Selector10~69 Selector2~255 Selector2~252 M0[2] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "11.400 ns" { S S~out Selector10~69 Selector2~255 Selector2~252 M0[2] } { 0.000ns 0.000ns 4.900ns 0.100ns 0.000ns 0.100ns } { 0.000ns 2.000ns 1.200ns 1.000ns 1.400ns 0.700ns } "" } } { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK M0[2] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.400 ns" { CLK CLK~out M0[2] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.400ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}