📄 jtdkz.sim.rpt
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; |JTDKZ|lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2] ; |JTDKZ|lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; data_out0 ;
; |JTDKZ|lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2] ; |JTDKZ|lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT ; cout ;
; |JTDKZ|MR~reg0 ; |JTDKZ|MR~reg0 ; data_out0 ;
; |JTDKZ|MY~reg0 ; |JTDKZ|MY~reg0 ; data_out0 ;
; |JTDKZ|MG~reg0 ; |JTDKZ|MG~reg0 ; data_out0 ;
; |JTDKZ|CR~reg0 ; |JTDKZ|CR~reg0 ; data_out0 ;
; |JTDKZ|CY~reg0 ; |JTDKZ|CY~reg0 ; data_out0 ;
; |JTDKZ|CG~reg0 ; |JTDKZ|CG~reg0 ; data_out0 ;
; |JTDKZ|LOAD ; |JTDKZ|LOAD ; data_out0 ;
; |JTDKZ|M0[2] ; |JTDKZ|M0[2] ; data_out0 ;
; |JTDKZ|LessThan0~34 ; |JTDKZ|LessThan0~34 ; data_out0 ;
; |JTDKZ|p2~60 ; |JTDKZ|p2~60 ; data_out0 ;
; |JTDKZ|lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~0 ; |JTDKZ|lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~0 ; data_out0 ;
; |JTDKZ|lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 ; |JTDKZ|lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 ; data_out0 ;
; |JTDKZ|M1[1] ; |JTDKZ|M1[1] ; data_out0 ;
; |JTDKZ|M1[2] ; |JTDKZ|M1[2] ; data_out0 ;
; |JTDKZ|MR1 ; |JTDKZ|MR1 ; data_out0 ;
; |JTDKZ|MY1 ; |JTDKZ|MY1 ; data_out0 ;
; |JTDKZ|MG1 ; |JTDKZ|MG1 ; data_out0 ;
; |JTDKZ|CY1 ; |JTDKZ|CY1 ; data_out0 ;
; |JTDKZ|CG1 ; |JTDKZ|CG1 ; data_out0 ;
; |JTDKZ|state.s2 ; |JTDKZ|state.s2 ; data_out0 ;
; |JTDKZ|p2~61 ; |JTDKZ|p2~61 ; data_out0 ;
; |JTDKZ|p2~1 ; |JTDKZ|p2~1 ; data_out0 ;
; |JTDKZ|Selector11~75 ; |JTDKZ|Selector11~75 ; data_out0 ;
; |JTDKZ|state.s0 ; |JTDKZ|state.s0 ; data_out0 ;
; |JTDKZ|Selector9~79 ; |JTDKZ|Selector9~79 ; data_out0 ;
; |JTDKZ|state.s3 ; |JTDKZ|state.s3 ; data_out0 ;
; |JTDKZ|state.s1 ; |JTDKZ|state.s1 ; data_out0 ;
; |JTDKZ|Selector5~164 ; |JTDKZ|Selector5~164 ; data_out0 ;
; |JTDKZ|Selector0~153 ; |JTDKZ|Selector0~153 ; data_out0 ;
; |JTDKZ|EN~22 ; |JTDKZ|EN~22 ; data_out0 ;
; |JTDKZ|Selector0~154 ; |JTDKZ|Selector0~154 ; data_out0 ;
; |JTDKZ|CNT0~388 ; |JTDKZ|CNT0~388 ; data_out0 ;
; |JTDKZ|CNT0~389 ; |JTDKZ|CNT0~389 ; data_out0 ;
; |JTDKZ|CNT0~390 ; |JTDKZ|CNT0~390 ; data_out0 ;
; |JTDKZ|Add1~69 ; |JTDKZ|Add1~69 ; data_out0 ;
; |JTDKZ|Selector7~155 ; |JTDKZ|Selector7~155 ; data_out0 ;
; |JTDKZ|Selector6~173 ; |JTDKZ|Selector6~173 ; data_out0 ;
; |JTDKZ|Selector10~68 ; |JTDKZ|Selector10~68 ; data_out0 ;
; |JTDKZ|Selector10~69 ; |JTDKZ|Selector10~69 ; data_out0 ;
; |JTDKZ|Selector2~250 ; |JTDKZ|Selector2~255 ; cascout ;
; |JTDKZ|Selector2~252 ; |JTDKZ|Selector2~252 ; data_out0 ;
; |JTDKZ|MR~3 ; |JTDKZ|MR~3 ; data_out0 ;
; |JTDKZ|CLK ; |JTDKZ|CLK~corein ; dataout ;
; |JTDKZ|S ; |JTDKZ|S~corein ; dataout ;
; |JTDKZ|CNT0[0] ; |JTDKZ|CNT0[0] ; padio ;
; |JTDKZ|CNT0[1] ; |JTDKZ|CNT0[1] ; padio ;
; |JTDKZ|CNT0[2] ; |JTDKZ|CNT0[2] ; padio ;
; |JTDKZ|CNT0[3] ; |JTDKZ|CNT0[3] ; padio ;
; |JTDKZ|CNT1[0] ; |JTDKZ|CNT1[0] ; padio ;
; |JTDKZ|CNT1[1] ; |JTDKZ|CNT1[1] ; padio ;
; |JTDKZ|CNT1[2] ; |JTDKZ|CNT1[2] ; padio ;
; |JTDKZ|MR ; |JTDKZ|MR ; padio ;
; |JTDKZ|MY ; |JTDKZ|MY ; padio ;
; |JTDKZ|MG ; |JTDKZ|MG ; padio ;
; |JTDKZ|CR ; |JTDKZ|CR ; padio ;
; |JTDKZ|CY ; |JTDKZ|CY ; padio ;
; |JTDKZ|CG ; |JTDKZ|CG ; padio ;
+--------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+------------------------------------------------------------------------------+-------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+------------------------------------------------------------------------------+-------------------------------------------------------------------+------------------+
; |JTDKZ|lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3] ; |JTDKZ|lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; data_out0 ;
; |JTDKZ|M1[0] ; |JTDKZ|M1[0] ; data_out0 ;
; |JTDKZ|CNT1[3] ; |JTDKZ|CNT1[3] ; padio ;
+------------------------------------------------------------------------------+-------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+------------------------------------------------------------------------------+-------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+------------------------------------------------------------------------------+-------------------------------------------------------------------+------------------+
; |JTDKZ|lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3] ; |JTDKZ|lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; data_out0 ;
; |JTDKZ|M1[0] ; |JTDKZ|M1[0] ; data_out0 ;
; |JTDKZ|EN ; |JTDKZ|EN ; data_out0 ;
; |JTDKZ|CNT1[3] ; |JTDKZ|CNT1[3] ; padio ;
+------------------------------------------------------------------------------+-------------------------------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
Info: Processing started: Thu Nov 29 22:08:08 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off JTDKZ -c JTDKZ
Info: Using vector source file "D:/EDA/traffic/JTDKZ.vwf"
Info: Inverted registers were found during simulation
Info: Register: |JTDKZ|MG~reg0
Info: Register: |JTDKZ|CR~reg0
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 94.29 %
Info: Number of transitions in simulation is 1368
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Allocated 91 megabytes of memory during processing
Info: Processing ended: Thu Nov 29 22:08:09 2007
Info: Elapsed time: 00:00:01
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