jtdkz.tan.rpt

一条主干道

; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1K100QI208-2     ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                  ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                       ; To                                                         ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 51.55 MHz ( period = 19.400 ns )                    ; lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; M0[2]                                                      ; CLK        ; CLK      ; None                        ; None                      ; 8.300 ns                ;
; N/A                                     ; 52.08 MHz ( period = 19.200 ns )                    ; lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; M0[2]                                                      ; CLK        ; CLK      ; None                        ; None                      ; 8.200 ns                ;
; N/A                                     ; 52.63 MHz ( period = 19.000 ns )                    ; lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; M0[2]                                                      ; CLK        ; CLK      ; None                        ; None                      ; 8.100 ns                ;
; N/A                                     ; 53.19 MHz ( period = 18.800 ns )                    ; CNT0[3]~reg0                                               ; M0[2]                                                      ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 53.19 MHz ( period = 18.800 ns )                    ; lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; M0[2]                                                      ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; CNT0[2]~reg0                                               ; M0[2]                                                      ; CLK        ; CLK      ; None                        ; None                      ; 7.900 ns                ;
; N/A                                     ; 54.35 MHz ( period = 18.400 ns )                    ; CNT0[1]~reg0                                               ; M0[2]                                                      ; CLK        ; CLK      ; None                        ; None                      ; 7.800 ns                ;
; N/A                                     ; 56.82 MHz ( period = 17.600 ns )                    ; CNT0[0]~reg0                                               ; M0[2]                                                      ; CLK        ; CLK      ; None                        ; None                      ; 7.400 ns                ;
; N/A                                     ; 57.47 MHz ( period = 17.400 ns )                    ; lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; LOAD                                                       ; CLK        ; CLK      ; None                        ; None                      ; 7.300 ns                ;
; N/A                                     ; 57.47 MHz ( period = 17.400 ns )                    ; CNT0[0]~reg0                                               ; M1[2]                                                      ; CLK        ; CLK      ; None                        ; None                      ; 7.300 ns                ;
; N/A                                     ; 58.14 MHz ( period = 17.200 ns )                    ; lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; LOAD                                                       ; CLK        ; CLK      ; None                        ; None                      ; 7.200 ns                ;
; N/A                                     ; 58.14 MHz ( period = 17.200 ns )                    ; lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; M1[0]                                                      ; CLK        ; CLK      ; None                        ; None                      ; 7.200 ns                ;
; N/A                                     ; 58.82 MHz ( period = 17.000 ns )                    ; lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; LOAD                                                       ; CLK        ; CLK      ; None                        ; None                      ; 7.100 ns                ;
; N/A                                     ; 58.82 MHz ( period = 17.000 ns )                    ; lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; M1[0]                                                      ; CLK        ; CLK      ; None                        ; None                      ; 7.100 ns                ;
; N/A                                     ; 58.82 MHz ( period = 17.000 ns )                    ; lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; M1[1]                                                      ; CLK        ; CLK      ; None                        ; None                      ; 7.100 ns                ;