jtdkz.map.rpt

一条主干道

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                         ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------+--------------+
; Compilation Hierarchy Node             ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                          ; Library Name ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------+--------------+
; |JTDKZ                                 ; 52 (46)     ; 29           ; 0           ; 16   ; 23 (21)      ; 9 (9)             ; 20 (16)          ; 4 (0)           ; 0 (0)      ; |JTDKZ                                                       ; work         ;
;    |lpm_counter:CNT1_rtl_0|            ; 6 (0)       ; 4            ; 0           ; 0    ; 2 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; 0 (0)      ; |JTDKZ|lpm_counter:CNT1_rtl_0                                ; work         ;
;       |alt_counter_f10ke:wysi_counter| ; 6 (6)       ; 4            ; 0           ; 0    ; 2 (2)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; 0 (0)      ; |JTDKZ|lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter ; work         ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+------------------------------------------------------+
; State Machine - |JTDKZ|state                         ;
+----------+----------+----------+----------+----------+
; Name     ; state.s3 ; state.s2 ; state.s1 ; state.s0 ;
+----------+----------+----------+----------+----------+
; state.s0 ; 0        ; 0        ; 0        ; 0        ;
; state.s1 ; 0        ; 0        ; 1        ; 1        ;
; state.s2 ; 0        ; 1        ; 0        ; 1        ;
; state.s3 ; 1        ; 0        ; 0        ; 1        ;
+----------+----------+----------+----------+----------+


+------------------------------------------------------------+
; Registers Removed During Synthesis                         ;
+---------------------------------------+--------------------+
; Register name                         ; Reason for Removal ;
+---------------------------------------+--------------------+
; M1[3]                                 ; Merged with M1[0]  ;
; M0[0..1,3]                            ; Merged with M1[0]  ;
; CR1                                   ; Merged with MR1    ;
; Total Number of Removed Registers = 5 ;                    ;
+---------------------------------------+--------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 29    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 4     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 11    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; MG~reg0                                ; 1       ;
; CR~reg0                                ; 1       ;
; Total number of inverted registers = 2 ;         ;
+----------------------------------------+---------+


+-----------------------------------------------+
; Source assignments for lpm_counter:CNT1_rtl_0 ;
+---------------------------+-------+------+----+
; Assignment                ; Value ; From ; To ;
+---------------------------+-------+------+----+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -  ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -  ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -  ;
+---------------------------+-------+------+----+


+-------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:CNT1_rtl_0 ;
+------------------------+-------------------+----------------------------+
; Parameter Name         ; Value             ; Type                       ;
+------------------------+-------------------+----------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                 ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY               ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE               ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE             ;
; LPM_WIDTH              ; 4                 ; Untyped                    ;
; LPM_DIRECTION          ; DOWN              ; Untyped                    ;
; LPM_MODULUS            ; 0                 ; Untyped                    ;
; LPM_AVALUE             ; UNUSED            ; Untyped                    ;
; LPM_SVALUE             ; UNUSED            ; Untyped                    ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                    ;
; DEVICE_FAMILY          ; ACEX1K            ; Untyped                    ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                    ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH         ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK         ;
; CARRY_CNT_EN           ; SMART             ; Untyped                    ;
; LABWIDE_SCLR           ; ON                ; Untyped                    ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                    ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                    ;
+------------------------+-------------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
    Info: Processing started: Thu Nov 29 22:51:37 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off JTDKZ -c JTDKZ
Info: Found 2 design units, including 1 entities, in source file JTDKZ.vhd
    Info: Found design unit 1: JTDKZ-behav
    Info: Found entity 1: JTDKZ
Info: Elaborating entity "JTDKZ" for the top level hierarchy
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "CNT1[0]~16"
Info: Found 1 design units, including 1 entities, in source file ../../quartus7.1/quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "lpm_counter:CNT1_rtl_0"
Info: Found 1 design units, including 1 entities, in source file ../../quartus7.1/quartus/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Elaborated megafunction instantiation "lpm_counter:CNT1_rtl_0|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "lpm_counter:CNT1_rtl_0"
Info: Instantiated megafunction "lpm_counter:CNT1_rtl_0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_DIRECTION" = "DOWN"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Duplicate registers merged to single register
    Info: Duplicate register "M1[3]" merged to single register "M1[0]"
    Info: Duplicate register "M0[0]" merged to single register "M1[0]"
    Info: Duplicate register "M0[1]" merged to single register "M1[0]"
    Info: Duplicate register "M0[3]" merged to single register "M1[0]"
    Info: Duplicate register "CR1" merged to single register "MR1", power-up level changed
Info: State machine "|JTDKZ|state" contains 4 states
Info: Selected Auto state machine encoding method for state machine "|JTDKZ|state"
Info: Encoding result for state machine "|JTDKZ|state"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "state.s3"
        Info: Encoded state bit "state.s2"
        Info: Encoded state bit "state.s1"
        Info: Encoded state bit "state.s0"
    Info: State "|JTDKZ|state.s0" uses code string "0000"
    Info: State "|JTDKZ|state.s1" uses code string "0011"
    Info: State "|JTDKZ|state.s2" uses code string "0101"
    Info: State "|JTDKZ|state.s3" uses code string "1001"
Info: Implemented 68 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 14 output pins
    Info: Implemented 52 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 152 megabytes of memory during processing
    Info: Processing ended: Thu Nov 29 22:51:44 2007
    Info: Elapsed time: 00:00:07