jtdkz.vhd

一条主干道

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity JTDKZ is
port(CLK,S:in std_logic;
     CNT0,CNT1:buffer std_logic_vector(3 downto 0);
     MR:OUT STD_LOGIC:='0';
     MY:OUT STD_LOGIC:='0';
     MG:OUT STD_LOGIC:='1';
     CR:OUT STD_LOGIC:='1';
     CY:OUT STD_LOGIC:='0';
     CG:OUT STD_LOGIC:='0');
end JTDKZ;

architecture behav of JTDKZ is
type states is(s0,s1,s2,s3);
signal state:states;
signal M0,M1:std_logic_vector(3 downto 0);
signal EN,T,LOAD:std_logic;
signal MR1,MY1,MG1,CR1,CY1,CG1:STD_LOGIC;
begin 

p1:process(CLK,EN,LOAD)
begin 
if CLK'event and CLK='0' then
 if EN='1' then
    if LOAD='1' then
      CNT0<=M0;CNT1<=M1;MR<=MR1;MY<=MY1;MG<=MG1;CR<=CR1;CY<=CY1;CG<=CG1;
    elsif LOAD='0' then
      if CNT1>0 then   
        if CNT0="0000" then 
          CNT1<=CNT1-1; CNT0<="1001";
        else CNT0<=CNT0-1;
        end if;
      elsif CNT1=0  then
        CNT0<=CNT0-1;
      end if;
    end if;
  end if;
end if;
end process;

p2:process(CLK)
begin
if CLK'event and CLK='1' then
 case state is
 when s0 =>MR1<='0';MY1<='1';MG1<='0';CR1<='1';CY1<='0';CG1<='0';
   if CNT0="0000" and CNT1="0000" then 
     if S='1' then 
      EN<='1';
      LOAD<='1';
      M0<="0100";
      M1<="0000";
      state<=s1;
     else EN<='0';
    end if;
   else LOAD<='0';
  end if;
 when s1 => MR1<='1';MY1<='0';MG1<='0';CR1<='0';CY1<='0';CG1<='1';
  if(CNT0="0001" and CNT1="0000") then 
     LOAD<='1';
     M1<="0010"; 
     M0<="0000";
     state<=s2;
   else LOAD<='0';
   end if;
 when s2 => MR1<='1';MY1<='0';MG1<='0';CR1<='0';CY1<='1';CG1<='0';
   if S='1' then
    if CNT0="0001" and CNT1="0000" then 
     LOAD<='1';
     M1<="0000"; 
     M0<="0100";
     state<=s3;
    else LOAD<='0';
    end if;
   else
     LOAD<='1';
     M1<="0000"; 
     M0<="0100";
     state<=s3;
   end if;
 when s3 => MR1<='0';MY1<='0';MG1<='1';CR1<='1';CY1<='0';CG1<='0';
   if CNT0="0001" and CNT1="0000" then 
     LOAD<='1';
     M1<="0110"; 
     M0<="0000";
     state<=s0;
    else LOAD<='0';
    end if;
 end case;
end if;
end process;
end behav;