ep931xide.cod

PXA270的BSP

; 478  :     {
; 479  : 	//RETAILMSG( 1, (TEXT("     * * * Unaligned copy in SetupDMA... * * *\r\n")));
; 480  :         ulDmaCount  = 0;

  00130	e3a04000	 mov         r4, #0

; 481  :         for (ulBuffer = 0; ulBuffer < dwSgCount; ulBuffer++) 

  00134	e3570000	 cmp         r7, #0
  00138	0a00000f	 beq         |$L33035|
  0013c		 |$L33033|

; 482  :         {
; 483  :             if(!fRead)

  0013c	e3580000	 cmp         r8, #0
  00140	1a000008	 bne         |$L33036|

; 484  :             {
; 485  : 			if (pSgBuf[ulBuffer].sb_len >0x8000 || pSgBuf[ulBuffer].sb_len <=0 || pBuffer == NULL || m_pucStaticBuffer == NULL)
; 486  : 				DEBUGMSG( 1, (TEXT("     * * * pSgBuf[ulBuffer].sb_len was %ld * * *\r\n"),pSgBuf[ulBuffer].sb_len));
; 487  : 
; 488  :             pBuffer = (LPBYTE)MapPtrToProcess(pSgBuf[ulBuffer].sb_buf, GetCallerProcess());

  00144	eb000000	 bl          GetCallerProcess
  00148	e1a01000	 mov         r1, r0
  0014c	e5960000	 ldr         r0, [r6]
  00150	eb000000	 bl          MapPtrToProcess

; 489  :             memcpy(m_pucStaticBuffer + ulDmaCount, pBuffer, pSgBuf[ulBuffer].sb_len);

  00154	e5953028	 ldr         r3, [r5, #0x28]
  00158	e5962004	 ldr         r2, [r6, #4]
  0015c	e1a01000	 mov         r1, r0
  00160	e0830004	 add         r0, r3, r4
  00164	eb000000	 bl          memcpy
  00168		 |$L33036|

; 490  :             }
; 491  :             ulDmaCount+= pSgBuf[ulBuffer].sb_len;

  00168	e5963004	 ldr         r3, [r6, #4]
  0016c	e2866008	 add         r6, r6, #8
  00170	e2577001	 subs        r7, r7, #1
  00174	e0844003	 add         r4, r4, r3
  00178	1affffef	 bne         |$L33033|
  0017c		 |$L33035|

; 492  :         }
; 493  :         m_ulDmaCount    = ulDmaCount;
; 494  :         m_pucDmaBuffer  = m_pucStaticBuffer;

  0017c	e5953028	 ldr         r3, [r5, #0x28]

; 495  :         m_ulDmaPhysBuff = m_ulStaticPhysBuff;

  00180	e595202c	 ldr         r2, [r5, #0x2C]
  00184	e5854038	 str         r4, [r5, #0x38]
  00188	e5853030	 str         r3, [r5, #0x30]
  0018c	e5852034	 str         r2, [r5, #0x34]
  00190		 |$L33032|

; 496  :     }
; 497  : 
; 498  : 	//* * * This is really stupid and not optimal. This should get tokenized
; 499  :     //* * * and placed in the PORT class.
; 500  : 
; 501  :     //* * * Setup DMA controller.
; 502  : 	m_pulDmaBase[M2M_CTRL>>2] |= M2M_CTRL_DONEINTEN;

  00190	e595200c	 ldr         r2, [r5, #0xC]

; 503  : 	m_pulDmaBase[M2M_CTRL>>2] |= M2M_CTRL_BWC_FULLTRANS; 
; 504  :     m_pulDmaBase[M2M_CTRL>>2] |= M2M_CTRL_PW_WORD;
; 505  :     m_pulDmaBase[M2M_CTRL>>2] |= M2M_CTRL_TM_SOFTINIT; 
; 506  :     m_pulDmaBase[M2M_CTRL>>2] |= M2M_CTRL_ETDP_AHIGH_OUTPUT; 
; 507  :     m_pulDmaBase[M2M_CTRL>>2] |= M2M_CTRL_DREQP_HIGHLEVEL;
; 508  :     m_pulDmaBase[M2M_CTRL>>2] |= M2M_CTRL_RSS_INTIDE; 
; 509  :     m_pulDmaBase[M2M_CTRL>>2] |= M2M_CTRL_NO_HDSK;
; 510  : 
; 511  : 	//* * * CAMSDB - Test for proper DMA channel setup. (START)
; 512  :     DumbCntrlRead = m_pulDmaBase[M2M_CTRL>>2]; //* * * According to SPEC>
; 513  : 	//* * * CAMSDB - Test for proper DMA channel setup. (END)
; 514  : 
; 515  :     //
; 516  :     // Setup the DMA ctrl register.
; 517  :     //
; 518  :     if(fRead)

  00194	e3580000	 cmp         r8, #0
  00198	e5923000	 ldr         r3, [r2]
  0019c	e3833004	 orr         r3, r3, #4
  001a0	e5823000	 str         r3, [r2]
  001a4	e595200c	 ldr         r2, [r5, #0xC]
  001a8	e5923000	 ldr         r3, [r2]
  001ac	e5823000	 str         r3, [r2]
  001b0	e595200c	 ldr         r2, [r5, #0xC]
  001b4	e5923000	 ldr         r3, [r2]
  001b8	e3833b01	 orr         r3, r3, #1, 22
  001bc	e5823000	 str         r3, [r2]
  001c0	e595200c	 ldr         r2, [r5, #0xC]
  001c4	e5923000	 ldr         r3, [r2]
  001c8	e5823000	 str         r3, [r2]
  001cc	e595200c	 ldr         r2, [r5, #0xC]
  001d0	e5923000	 ldr         r3, [r2]
  001d4	e3833906	 orr         r3, r3, #6, 18
  001d8	e5823000	 str         r3, [r2]
  001dc	e595200c	 ldr         r2, [r5, #0xC]
  001e0	e5923000	 ldr         r3, [r2]
  001e4	e3833702	 orr         r3, r3, #2, 14
  001e8	e5823000	 str         r3, [r2]
  001ec	e595200c	 ldr         r2, [r5, #0xC]
  001f0	e5923000	 ldr         r3, [r2]
  001f4	e3833503	 orr         r3, r3, #3, 10
  001f8	e5823000	 str         r3, [r2]
  001fc	e595200c	 ldr         r2, [r5, #0xC]
  00200	e5923000	 ldr         r3, [r2]
  00204	e3833401	 orr         r3, r3, #1, 8
  00208	e5823000	 str         r3, [r2]
  0020c	e595200c	 ldr         r2, [r5, #0xC]
  00210	e5923000	 ldr         r3, [r2]
  00214	e58d3000	 str         r3, [sp]

; 519  :     {
; 520  :         //* * * Original = m_ulDmaCtrlReg    = M2M_CTRL_SAH | M2M_CTRL_TM_HARDINITP2M;
; 521  : 		m_pulDmaBase[M2M_CTRL>>2] |=M2M_CTRL_SAH;

  00218	e5923000	 ldr         r3, [r2]
  0021c	13833a01	 orrne       r3, r3, #1, 20
  00220	15823000	 strne       r3, [r2]

; 522  : 		m_pulDmaBase[M2M_CTRL>>2] |=M2M_CTRL_TM_HARDINITP2M;

  00224	1595200c	 ldrne       r2, [r5, #0xC]
  00228	15923000	 ldrne       r3, [r2]
  0022c	13833901	 orrne       r3, r3, #1, 18

; 523  : 		m_pulDmaBase[M2M_CTRL>>2] |=M2M_CTRL_NO_HDSK;
; 524  : 
; 525  :     }
; 526  :     else
; 527  :     {
; 528  : 		//* * * Original = m_ulDmaCtrlReg    = M2M_CTRL_DAH | M2M_CTRL_TM_HARDINITM2P;
; 529  : 		m_pulDmaBase[M2M_CTRL>>2] |=M2M_CTRL_DAH;

  00230	03833b02	 orreq       r3, r3, #2, 22
  00234	05823000	 streq       r3, [r2]

; 530  : 		m_pulDmaBase[M2M_CTRL>>2] |=M2M_CTRL_TM_HARDINITM2P;

  00238	0595200c	 ldreq       r2, [r5, #0xC]
  0023c	05923000	 ldreq       r3, [r2]
  00240	03833a02	 orreq       r3, r3, #2, 20
  00244	e5823000	 str         r3, [r2]

; 531  : 		m_pulDmaBase[M2M_CTRL>>2] |=M2M_CTRL_NO_HDSK;

  00248	e595200c	 ldr         r2, [r5, #0xC]
  0024c	e5923000	 ldr         r3, [r2]
  00250	e3833401	 orr         r3, r3, #1, 8
  00254	e5823000	 str         r3, [r2]

; 532  :     }
; 533  : 
; 534  : 	//* * * CAMSDB - Test for proper DMA channel setup. (START)
; 535  :     DumbCntrlRead = m_pulDmaBase[M2M_CTRL>>2]; //* * * According to SPEC>

  00258	e595100c	 ldr         r1, [r5, #0xC]

; 536  : 	//* * * CAMSDB - Test for proper DMA channel setup. (END)
; 537  : 
; 538  :     //
; 539  :     // Setup the source and destination with there proper values.
; 540  :     //
; 541  :     switch(m_ulCurrentMode)

  0025c	e5952008	 ldr         r2, [r5, #8]
  00260	e5913000	 ldr         r3, [r1]
  00264	e3520a01	 cmp         r2, #1, 20
  00268	e58d3000	 str         r3, [sp]
  0026c	8a000019	 bhi         |$L33840|
  00270	0a00001e	 beq         |$L33048|
  00274	e3520c01	 cmp         r2, #1, 24
  00278	0a000013	 beq         |$L33047|
  0027c	e3520c02	 cmp         r2, #2, 24
  00280	0a000011	 beq         |$L33047|
  00284	e3520b01	 cmp         r2, #1, 22
  00288	0a00000f	 beq         |$L33047|
  0028c	e3520b02	 cmp         r2, #2, 22
  00290	0a000016	 beq         |$L33048|
  00294		 |$L33848|
  00294	e59de000	 ldr         lr, [sp]
  00298	e59d0000	 ldr         r0, [sp]
  0029c		 |$L33044|

; 578  :     }
; 579  : 
; 580  : 	//* * * CAMSDB - Test for proper DMA channel setup. (START)
; 581  : 	DumbCntrlRead = m_pulDmaBase[M2M_CTRL>>2]; //* * * According to SPEC>

  0029c	e595200c	 ldr         r2, [r5, #0xC]

; 582  : 	//* * * CAMSDB - Test for proper DMA channel setup. (END)
; 583  : 
; 584  :     //
; 585  :     // Clear the status register.
; 586  :     //
; 587  :     m_pulDmaBase[M2M_STATUS>>2] = 0;
; 588  : 
; 589  :     //
; 590  :     // Bit definitions are the same for Udma and Mdma.
; 591  :     //
; 592  :     if(fRead)

  002a0	e3580000	 cmp         r8, #0
  002a4	e5923000	 ldr         r3, [r2]
  002a8	e58d3000	 str         r3, [sp]
  002ac	e582a00c	 str         r10, [r2, #0xC]
  002b0	0a000014	 beq         |$L33051|

; 593  :     {
; 594  :         m_pulDmaBase[M2M_SAR_BASE0>>2] = ulIDESource;        

  002b4	e595300c	 ldr         r3, [r5, #0xC]
  002b8	e5830018	 str         r0, [r3, #0x18]

; 595  :         m_pulDmaBase[M2M_DAR_BASE0>>2] = m_ulDmaPhysBuff;       

  002bc	e595200c	 ldr         r2, [r5, #0xC]
  002c0	e5953034	 ldr         r3, [r5, #0x34]
  002c4	e582302c	 str         r3, [r2, #0x2C]

; 596  :     }
; 597  :     else

  002c8	ea000013	 b           |$L33052|
  002cc		 |$L33047|

; 542  :     {
; 543  :         case MWDMA_MODE0:
; 544  :         case MWDMA_MODE1:
; 545  :         case MWDMA_MODE2:
; 546  :             //* * * Original  = m_ulDmaCtrlReg |= (fRead?3:3)<<M2M_CTRL_PWSC_SHIFT;
; 547  : 			m_pulDmaBase[M2M_CTRL>>2] |= (fRead?3:3)<<M2M_CTRL_PWSC_SHIFT;
; 548  : 			ulIDESource = 0x800a001C; 

  002cc	e59f0088	 ldr         r0, [pc, #0x88]

; 549  :             ulIDEDest   = 0x800a0018; 

  002d0	e59fe080	 ldr         lr, [pc, #0x80]

; 550  :             break;

  002d4	ea000007	 b           |$L33863|
  002d8		 |$L33840|

; 536  : 	//* * * CAMSDB - Test for proper DMA channel setup. (END)
; 537  : 
; 538  :     //
; 539  :     // Setup the source and destination with there proper values.
; 540  :     //
; 541  :     switch(m_ulCurrentMode)

  002d8	e3520a02	 cmp         r2, #2, 20
  002dc	0a000003	 beq         |$L33048|
  002e0	e3520901	 cmp         r2, #1, 18
  002e4	0a000001	 beq         |$L33048|
  002e8	e3520902	 cmp         r2, #2, 18

; 568  :             break;
; 569  :         default:
; 570  :             DEBUGMSG
; 571  :             ( 
; 572  :                 1, 
; 573  :                 (
; 574  :                     TEXT("ATAPI:SetupDMA EP9312 unsupported dma mode.\r\n")
; 575  :                 )
; 576  :             );
; 577  :             break;

  002ec	1affffe8	 bne         |$L33848|
  002f0		 |$L33048|

; 551  :         case UDMA_MODE0:
; 552  :         case UDMA_MODE1:
; 553  :         case UDMA_MODE2:
; 554  :         case UDMA_MODE3:
; 555  :         case UDMA_MODE4:
; 556  :             //* * * Original = m_ulDmaCtrlReg |= (fRead?1:2)<<M2M_CTRL_PWSC_SHIFT;
; 557  : 
; 558  : 		    //* * * The timing below is the only reliable one that will work.
; 559  : 			//* * * More research needs to be done as to why...(START)
; 560  : 		
; 561  : 			m_pulDmaBase[M2M_CTRL>>2] |= (fRead?3:3)<<M2M_CTRL_PWSC_SHIFT;
; 562  : 
; 563  : 		    //* * * The timing above is the only reliable one that will work.
; 564  : 			//* * * More research needs to be done as to why...(END)
; 565  : 
; 566  : 			ulIDESource = 0x800a0024; 

  002f0	e59f005c	 ldr         r0, [pc, #0x5C]

; 567  : 			ulIDEDest   = 0x800a0020; 

  002f4	e59fe054	 ldr         lr, [pc, #0x54]
  002f8		 |$L33863|
  002f8	e5913000	 ldr         r3, [r1]
  002fc	e3833406	 orr         r3, r3, #6, 8
  00300	e5813000	 str         r3, [r1]
  00304	eaffffe4	 b           |$L33044|
  00308		 |$L33051|

; 598  :     {
; 599  :         m_pulDmaBase[M2M_SAR_BASE0>>2] = m_ulDmaPhysBuff;       

  00308	e595200c	 ldr         r2, [r5, #0xC]
  0030c	e5953034	 ldr         r3, [r5, #0x34]
  00310	e5823018	 str         r3, [r2, #0x18]

; 600  :         m_pulDmaBase[M2M_DAR_BASE0>>2] = ulIDEDest;       

  00314	e595300c	 ldr         r3, [r5, #0xC]
  00318	e583e02c	 str         lr, [r3, #0x2C]
  0031c		 |$L33052|

; 601  :     }
; 602  : 
; 603  :     //
; 604  :     // Figure out the number of bytes to transfer. Round up.
; 605  :     //
; 606  : 
; 607  : 	//* * * This is needed for MDMA modes for CD/DVD drives.
; 608  : 	//* * * Probably not needed anymore...
; 609  : 	if (m_ulDmaCount >= 0x10000)

  0031c	e5953038	 ldr         r3, [r5, #0x38]

; 610  : 		m_ulDmaCount = 0xFFFC;
; 611  : 
; 612  : 	m_pulDmaBase[M2M_BCR0>>2] = m_ulDmaCount;

  00320	e595200c	 ldr         r2, [r5, #0xC]

; 613  : 
; 614  : 	//
; 615  :     // The IDE controller is now using DMA, yay sure Ron...
; 616  :     //
; 617  :     m_bDMAState = TRUE;
; 618  :  
; 619  :     return TRUE;

  00324	e3a00001	 mov         r0, #1
  00328	e3530801	 cmp         r3, #1, 16
  0032c	23a03cff	 movcs       r3, #0xFF, 24
  00330	238330fc	 orrcs       r3, r3, #0xFC
  00334	25853038	 strcs       r3, [r5, #0x38]
  00338	e5953038	 ldr         r3, [r5, #0x38]
  0033c	e5823010	 str         r3, [r2, #0x10]
  00340	e585b004	 str         r11, [r5, #4]

; 620  : }

  00344	e28dd048	 add         sp, sp, #0x48
  00348	e8bd4ff0	 ldmia       sp!, {r4 - r11, lr}
  0034c	e12fff1e	 bx          lr
  00350		 |$L33869|
  00350	800a0020	 DCD         0x800a0020
  00354	800a0024	 DCD         0x800a0024
  00358	800a0018	 DCD         0x800a0018
  0035c	800a001c	 DCD         0x800a001c
  00360		 |$M33865|

			 ENDP  ; |?SetupDMA@CEP931xPort@@QAAHPAU_SG_BUF@@KHK@Z|, CEP931xPort::SetupDMA

	EXPORT	|?EndDMA@CEP931xPort@@QAAHXZ|		; CEP931xPort::EndDMA

  00000			 AREA	 |.text| { |?EndDMA@CEP931xPort@@QAAHXZ| }, CODE, ARM, SELECTION=1 ; comdat noduplicate

  00000			 AREA	 |.pdata$$?EndDMA@CEP931xPort@@QAAHXZ|, PDATA, SELECTION=5, ASSOC=|.text| { |?EndDMA@CEP931xPort@@QAAHXZ| } ; comdat associative
|$T33878| DCD	|$L33877|
	DCD	0x40000f02
; Function compile flags: /Ogsy

  00000			 AREA	 |.text| { |?EndDMA@CEP931xPort@@QAAHXZ| }, CODE, ARM, SELECTION=1 ; comdat noduplicate

  00000		 |?EndDMA@CEP931xPort@@QAAHXZ| PROC	; CEP931xPort::EndDMA