📄 com.h
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#ifndef _COM_H
#define _COM_H
/*********************************************************************
* Filename: Com.h *
* *
* Author: Wang Heng, Shandong University,China. *
* *
* Last Modified: 06/01/03 *
* *
* Description: Servovalve Control System main program *
*********************************************************************/
#include "f2407_c.h"
//////////////////////////////////////////
typedef unsigned short BOOL;
typedef unsigned int BYTE;
typedef unsigned short WORD;
typedef unsigned long DWORD;
#define TRUE 1
#define FALSE 0
#define PI 3.14159265
#define PI_2 6.28318530
/*external resources address mapping to IOSpace*/
#define DOUT port0010
ioport unsigned int port0010;
#define DIN port0020
ioport unsigned int port0020;
#define LED port0040
ioport unsigned int port0040;
#define ADC_RESULT_H port0060
ioport unsigned int port0060;
#define ADC_RESULT_L port0070
ioport unsigned int port0070;
/* */
#define Z_IDX_MAX 50
#define C_IDX_MAX 200
/* CONTROL PERIOD */
#define SERVO_CYCLE 8000 /* GPTimer1, CLK=40MHZ, 200US-5KHZ, 40MHZ/(5KHZ)*/
#define PLC_CYCLE 5 /* Multiplation of SERVO_CYCLE*/
#define SERVO_PERIOD 0.0002 /* 200US */
#define SERVO_PERIOD_MOD 5000
/* initialization phase */
#define PHASE_CALL 0x01
#define PHASE_CONFIG 0x02
#define PHASE_OPERATION 0x03
#define PHASE_WAIT 0x04
/* call status */
#define CALL_IDLE 0x00
#define CALL_NORMAL 0x01
#define CALL_DECOM 0x02
/* configuration status */
#define CONFIG_IDLE 0x00
#define CONFIG_TRANS 0x01
#define CONFIG_DECOM 0x02
/* CONTROL MODES */
#define MODE_IDLE 0
#define MODE_AUTO 1
#define MODE_HOME 2
#define MODE_TUNE 3
typedef struct
{
unsigned short QepCnt;
unsigned short QepCntLast;
int QepDir;
//unsigned short EncLines;
//unsigned short EncMultiFreq;
unsigned short ExtEncLines;
} NP_EncoderTableVar, *NP_PEncoderTableVar;
/*typedef struct
{
long EncLine;
} NP_MotorPara;*/
typedef struct
{
unsigned short EncLines;
unsigned short EncMultiFreq;
} NP_EncoderPara;
typedef struct
{
int adc_bias;
int adc_offset;
} NP_ADCPara;
typedef struct
{
/*gain*/
long Kopen; /*open loop gain*/
WORD Kp; /*proportion gain*/
int IM; /*integration mode*/
WORD Ki; /*integration gain*/
WORD Kd; /*differential gain*/
WORD Kvff; /*velocity feed forward*/
WORD Kaff; /*acceleration feed forward*/
/*bias, limits and deadband*/
WORD DBfe; /*following error deadband*/
WORD BSfe; /*following error big step limits*/
DWORD LMTfei; /*following error integration limits*/
WORD LMTdac; /*dac output limit*/
int BIASdac;/*dac bias,+/-*/
} NP_PIDPara;
/*typedef struct
{
} NP_UserPara;*/
typedef struct
{
NP_EncoderPara v_EncParaZ;
NP_EncoderPara v_EncParaC;
NP_ADCPara v_ADCPara;
} NP_MechPara;
typedef struct
{
NP_PIDPara v_PIDPara;
} NP_SysPara;
/****************************************/
/* IDN macros */
#define IDN_PTN_MODE_IDLE 0x8070
#define IDN_PTN_MODE_AUTO 0x8071
#define IDN_PTN_MODE_HOME 0x8072
#define IDN_PTN_MODE_TUNE 0x8073
#define IDN_PTN_CYCRUN 0x8081
#define IDN_PTN_CYCSTOP 0x8082
#define IDN_PTN_ESTOP 0x8083
#define IDN_PTN_HOME 0x8091
#define IDN_PTN_TUNERUN 0x80A1
#define IDN_PTN_TUNESTOP 0x80A2
#define IDN_PTN_SAMPLERUN 0x80A3
#define IDN_PTN_SAMPLESTOP 0x80A4
#define IDN_PTN_SAMPDAT_UL 0x80A9
#define IDN_PTN_SIG_TYPE 0x80B0
#define IDN_PTN_SIG_STEP_SIZE 0x80B1
#define IDN_PTN_SIG_STEP_TIME 0x80B2
#define IDN_PTN_SIG_SIN_AMP 0x80B9
#define IDN_PTN_SIG_SIN_FREQ 0x80BA
#define IDN_PTN_SIG_SIN_RPT 0x80BB
#define IDN_PTN_TABLE_Z 0x80C1
#define IDN_PTN_TABLE_C_000 0x80D0
#define IDN_PTN_TABLE_C_001 0x80D1
#define IDN_PTN_TABLE_C_002 0x80D2
#define IDN_PTN_TABLE_C_003 0x80D3
#define IDN_PTN_TABLE_C_004 0x80D4
#define IDN_PTN_TABLE_C_005 0x80D5
#define IDN_PTN_TABLE_C_006 0x80D6
#define IDN_PTN_TABLE_C_007 0x80D7
#define IDN_PTN_TABLE_C_008 0x80D8
#define IDN_PTN_TABLE_C_009 0x80D9
#define IDN_PTN_TABLE_C_010 0x80DA
#define IDN_PTN_TABLE_C_011 0x80DB
#define IDN_PTN_TABLE_C_012 0x80DC
#define IDN_PTN_TABLE_C_013 0x80DD
#define IDN_PTN_TABLE_C_014 0x80DE
#define IDN_PTN_TABLE_C_015 0x80DF
#define IDN_PTN_TEST 0x8A79
/****************************************/
/* exchage data structure */
typedef union
{
unsigned short u_word[2];
short s_word[2];
unsigned long u_dword;
long s_dword;
float f_var;
char s_byte[4];
unsigned char u_byte[4];
} N_NRTData_Union;
typedef struct
{
unsigned short control_word;
N_NRTData_Union NRTData;
} N_NRTMDM;
typedef struct
{
unsigned short status_word;
N_NRTData_Union NRTData;
} N_NRTADM;
#define CW_ACT_EN 1
#define CW_ACT_DISEN 0
#define CW_DATAM_NONE 0x00
#define CW_DATAM_IDN 0x01
#define CW_DATAM_DATA 0x02
#define CW_TRANSFERRING 0
#define CW_TRANS_LAST 1
#define CW_READ 0
#define CW_WRITE 1
typedef struct
{
int actuator_enable; /* bit 7 */
int data_member; /* bit 4,3 */
int transferring; /* bit 2 */
int r_or_w; /* bit 1 */
int mhs; /* bit 0 */
} N_ControlWord;
#define SW_ACT_RDY 1
#define SW_ACT_NORDY 0
#define SW_ACT_NOSD 0 /* SHUT DOWN */
#define SW_ACT_SD 1
#define SW_NRTCH_NORM 0
#define SW_NRTCH_ERR 1
#define SW_NOBUSY 0
#define SW_BUSY 1
typedef struct
{
int actuator_ready; /* bit 7 */
int actuator_status; /* bit 6 */
int channel_status; /* bit 2 */
int busy; /* bit 1 */
int ahs; /* bit 0 */
} N_StatusWord;
//////////////////////////////////////////////////////////////////////////
/* OX16c950 Standard Registers offset */
#define THR_OFFSET portC000 /* Transmitter Holding Register(W) */
ioport unsigned int portC000;
#define RHR_OFFSET portC000 // Receiver Holding Register(R)
ioport unsigned int portC000;
#define IER_OFFSET portC001 // Interrupt Enable Register(R/W)
ioport unsigned int portC001;
#define FCR_OFFSET portC002 // FIFO Control Register(W)
ioport unsigned int portC002;
#define ISR_OFFSET portC002 // Interrupt Status Register(R)
ioport unsigned int portC002;
#define LCR_OFFSET portC003 // Line Control Register(R/W)
ioport unsigned int portC003;
#define MCR_OFFSET portC004 // Modem Control Register(R/W)
ioport unsigned int portC004;
#define LSR_OFFSET portC005 // Line Status Register(R)
ioport unsigned int portC005;
#define MSR_OFFSET portC006 // Modem Status Register(R)
ioport unsigned int portC006;
#define SPR_OFFSET portC007 // Scratch Pad Register(R/W)
ioport unsigned int portC007;
#define DLL_OFFSET portC000 // Divisor Latch Low-byte
ioport unsigned int portC000;
#define DLM_OFFSET portC001 // Divisor Latch High-byte
ioport unsigned int portC001;
/* OX16PCI954 650 Compatible Registers offset */
#define EFR_OFFSET portC002 // Enhanced Features Register(R/W)
ioport unsigned int portC002;
#define XON1_OFFSET portC004 // XON1 Flow control character(R/W)
ioport unsigned int portC004;
#define XON2_OFFSET portC005 // XON2 Flow control character(R/W)
ioport unsigned int portC005;
#define XOFF1_OFFSET portC006 // XOFF1 Flow control character(R/W)
ioport unsigned int portC006;
#define XOFF2_OFFSET portC007 // XOFF2 Flow control character(R/W)
ioport unsigned int portC007;
/* OX16PCI954 950 Specific Register offset */
#define ASR_OFFSET portC001 // Additional Status Register(R/W)
ioport unsigned int portC001;
#define RFL_OFFSET portC003 // Receiver FIFO Fill Level(0-128)(R)
ioport unsigned int portC003;
#define TFL_OFFSET portC004 // Transmitter FIFO Fill Level(0-128)(R)
ioport unsigned int portC004;
#define ICR_OFFSET portC005 // Indexed Control Register set common access point(R/W)
ioport unsigned int portC005;
#define RST_950 portA000 // Indexed Control Register set common access point(R/W)
ioport unsigned int portA000;
#define Port_2000 port2000 // Indexed Control Register set common access point(R/W)
ioport unsigned int port2000;
/* OX16PCI954 950 Indexed control Register Set offset */
#define ACR_OFFSET 0x00 // Advanced Control Register(R/W)
#define CPR_OFFSET 0x01 // Clock Prescaler Register(R/W)
#define TCR_OFFSET 0x02 // Times Clock Register(R/W)
#define CKS_OFFSET 0x03 // Clock Source Register(R/W)
#define TTL_OFFSET 0x04 // Transmitter Trigger Level(R/W)
#define RTL_OFFSET 0x05 // Receiver Trigger Level(R/W)
#define FCL_OFFSET 0x06 // Flow Control Low Trigger Level(R/W)
#define FCH_OFFSET 0x07 // Flow Control High Trigger Level(R/W)
#define ID1_OFFSET 0x08 // Identification Register 1(R)
#define ID2_OFFSET 0x09 // Identification Register 2(R)
#define ID3_OFFSET 0x0A // Identification Register 3(R)
#define REV_OFFSET 0x0B // Revision Identification Register(R)
#define CSR_OFFSET 0x0C // Channel Reset Register(W)
#define NMR_OFFSET 0x0D // Nine bit Mode Register(R/W)
/* the following is for FIFO control */
#define FCR_FIFO_EN 0x01
#define FCR_FLUSH_RHR 0x02
#define FCR_FLUSH_THR 0x04
#define FCR_TX_TRILVL_EN 0x08
#define FCR_RHR_TRILVL_1 0x00
#define FCR_RHR_TRILVL_4 0x40
#define FCR_RHR_TRILVL_8 0x80
#define FCR_RHR_TRILVL_14 0xC0
/* the following is for modem control */
#define MCR_DTR 0x01
#define MCR_RTS 0x02
#define MCR_OUT1 0x04
#define MCR_OUT2 0x08
/* the following is for reading FIFO levels */
#define RECEIVE_FIFO 0
#define TRANSMIT_FIFO 1
#define RXFIFO_MAX 128
#define TXFIFO_MAX 128
/* The following is for data framing mode (i.e. parity,stop,bits etc) */
#define LCR_5_BIT_DATA 0x00
#define LCR_6_BIT_DATA 0x01
#define LCR_7_BIT_DATA 0x02
#define LCR_8_BIT_DATA 0x03
#define LCR_1_STOP_BIT 0x00
#define LCR_1_5_STOP_BITS 0x04
#define LCR_2_STOP_BITS 0x04
#define LCR_NO_PARITY 0x00
#define LCR_ODD_PARITY 0x08
#define LCR_EVEN_PARITY 0x18
#define LCR_FORCE_HIGH_PARITY 0x28
#define LCR_FORCE_LOW_PARITY 0x38
#define LCR_FORCE_BREAK 0x40
#define LCR_MODE_8N2 LCR_8_BIT_DATA | LCR_2_STOP_BITS | LCR_NO_PARITY
#define LCR_MODE_8E1 LCR_8_BIT_DATA | LCR_1_STOP_BIT | LCR_EVEN_PARITY
#define LCR_MODE_8O1 LCR_8_BIT_DATA | LCR_1_STOP_BIT | LCR_ODD_PARITY
#define LCR_MODE_7E2 LCR_7_BIT_DATA | LCR_2_STOP_BITS | LCR_EVEN_PARITY
#define LCR_MODE_7O2 LCR_7_BIT_DATA | LCR_2_STOP_BITS | LCR_ODD_PARITY
#define LCR_MODE_5E1_5 LCR_5_BIT_DATA | LCR_1_5_STOP_BITS | LCR_EVEN_PARITY
/* The Line Status */
#define LSR_PARITY_ERROR 0x04
/* The Enhanced Features */
#define EFR_SPECIAL_CHR_EN 0x20
/* The Additional Status */
#define ASR_SPECIAL_CHR_DET 0x10
/* The Interrupt Enable */
#define IER_CHR_INTERRUPT_EN 0x20
#define LCR_DL_ACCESS_KEY 0x80
#define LCR_650_ACCESS_KEY 0xBF
#define ACR_INDEX 0x00
#define ACR_ICR_READ_EN 0x40
#define ACR_950_READ_EN 0x80
#define EFR_ENHANCED_MODE_EN 0x10
#define MCR_PRESCALER_EN 0x80
#define ACR_950_TRIGGER_EN 0x20
#define ACR_RX_DISABLE 0x01
#define ACR_TX_DISABLE 0x02
/* interrupt status */
#define ISR_STATUS_ERROR 0x06
#define ISR_DATA_AVALIABLE 0x04
#define ISR_RCV_TIMEOUT 0x0C
#define SEND_ENABLE 0x80
#define CONFIG_OUT 0x01
#define ADC_START 0x02
#define RESET_950 0x01
/* UART DEVICE */
typedef struct
{
BYTE shadowACR;
BYTE shadowFCR;
BYTE isr_val;
} NP_UART_DEV;//, PNP_UART_DEV;
typedef struct{
unsigned int ProcessT;
unsigned int SendT;
unsigned int Step;
} Time_Struct;
extern WORD N_ReadDivisor();
extern void N_WriteDivisor(WORD divisor);
extern BYTE N_Read650(WORD offset);
extern void N_Write650(WORD offset, BYTE value);
extern BYTE N_ReadICR(BYTE index);
extern void N_WriteICR(BYTE index, BYTE value);
extern void N_UnlockAdditionalStatus();
extern void N_LockAdditionalStatus();
extern BYTE N_ReadASR();
extern void N_WriteASRBit(BYTE asrbit, BOOL value);
extern BYTE N_ReadFIFOLevel(BYTE fifo);
extern void N_SetPrescalerEnable(BOOL state);
extern void N_Set950TriggerEnable(BOOL state);
extern void N_SetReceiverEnable(BOOL state);
extern void N_SetTransmitterEnable(BOOL state);
extern void dispatch_storage();
extern void store_interp_table();
extern void store_user_para();
extern void store_mech_para();
extern void store_sys_para();
extern void store_cmd();
extern void store_handshake();
extern void store_tune_sig();
extern void SendOutData();
#endif/*_COM_H*/
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