com.c

用ＴＭＳ３２０ＬＦ２４０７Ａ开发电机控制的源代码

* _Input: register index: BYTE index
* Returns: BYTE value read from indexed register
**************************************************************/ 

void N_WriteDivisor (WORD divisor)
{
	BYTE oldLCR;
	// Store the current value of LCR and then set the top bit to
	// allow divisor latch access

	oldLCR = LCR_OFFSET;
	LCR_OFFSET = oldLCR | LCR_DL_ACCESS_KEY;
	// Write the divisor latch word then restore LCR
	DLL_OFFSET = divisor & 0x00FF;
	DLM_OFFSET = (divisor & 0xFF00) >> 8;
	LCR_OFFSET = oldLCR;
}

BYTE N_Read650 (unsigned short offset)
{
	BYTE result, oldLCR;
	// Store the current LCR then write the access code
	oldLCR = LCR_OFFSET;
	LCR_OFFSET = LCR_650_ACCESS_KEY;
	// Read the register
	result = offset;
	// restore LCR and return the result
	LCR_OFFSET = oldLCR;

	return result;
}

void N_Write650 (unsigned short offset, BYTE value)
{
	BYTE oldLCR;
	// Store the current LCR then write the access code
	oldLCR = LCR_OFFSET;
	LCR_OFFSET = LCR_650_ACCESS_KEY;
	// Write the register
	offset = value;
	// Restore LCR
	LCR_OFFSET = oldLCR;
}

/*************************************************************
* Function: N_WriteICR (BYTE index, BYTE value)
* Description: Write the ICR set register indexed by the 'index'
* parameter with 'value'
* Parameters:
* _Input: register index: BYTE index
*         the value to be set: BYTE value
* Returns: none
**************************************************************/
/* Writing to ICR registers
*  Ensure that the last value written to LCR was not 0xBF
*  Write the desired offset to SPR
*  Write the desired value to ICR 
**************************************************************/
void N_WriteICR (BYTE index, BYTE value)
{	
	/* ICR acts as a window through which to read and
	   write registers in the indexed control register set*/
	SPR_OFFSET = index;
	ICR_OFFSET = value;
	// Record changes made to ACR
	if (index == ACR_INDEX)
	{
		uart_dev.shadowACR = value;
	}
}

/*************************************************************
* Function: N_ReadICR (BYTE index)
* Description: Reads the ICR set register indexed by the index 
* parameter with value.
* Parameters:
* _Input: register index: BYTE index
* Returns: BYTE value read from indexed register
**************************************************************/
/* Read from ICR registers
*  Ensure that the last value written to LCR was not 0xBF
*  Write 0x00 offset to SPR to select ACR
*  Set bit 6 of ACR by writing x1xxxxxx to address 101(ICR).
*  Ensure that other bits in ACR was not changed.
*  Write the desired offset to SPR
*  Read the desired value from ICR 
*  Write 0x00 offset to SPR to select ACR
*  Clear bit 6 of ACR, thus enabling access to standard registers again.
**************************************************************/ 
BYTE N_ReadICR (BYTE index)
{
	/* ICR acts as a window through which to read and
	   write registers in the indexed control register set*/
	BYTE retVal;
	// Enable read access
	// Read ICR ACR[6] must be 1
	N_WriteICR(ACR_INDEX, uart_dev.shadowACR | ACR_ICR_READ_EN); 
	SPR_OFFSET = index;
	retVal = ICR_OFFSET;
	// Disable read access
	N_WriteICR(ACR_INDEX, uart_dev.shadowACR & ~ACR_ICR_READ_EN);

	return retVal;
}

void N_UnlockAdditionalStatus ()
{
	// Set the top bit of ACR to enable 950 specific register set access
	uart_dev.shadowACR |= ACR_950_READ_EN;
	N_WriteICR(ACR_INDEX, uart_dev.shadowACR);
}

void N_LockAdditionalStatus ()
{
	// Clear the top bit of ACR to disable 950 specific register set access
	uart_dev.shadowACR &= ~ACR_950_READ_EN;
	N_WriteICR(ACR_INDEX, uart_dev.shadowACR);
}

BYTE N_ReadASR()
{
	BYTE retVal;
	N_UnlockAdditionalStatus ();
	retVal = ASR_OFFSET;
	N_LockAdditionalStatus ();

	return retVal;
}

void N_WriteASRBit (BYTE asrbit, BOOL value)
{
	// Set the specified ASR bit to 1 if value = TRUE 0 if value = FALSE
	BYTE currentASR;
	if ((0 == asrbit) || (1 == asrbit))  //Only allow writable bits to be set
        {
		N_UnlockAdditionalStatus ();
		currentASR = ASR_OFFSET;
		if (value)
		{
			// OR bit in if setting
			currentASR |= (1 << asrbit);
		}
		else
		{
			// Mask bit out if clearing
			currentASR &= ~(1 << asrbit);
		}
		ASR_OFFSET = currentASR;
		N_LockAdditionalStatus();
         }
}

BYTE N_ReadFIFOLevel (BYTE fifo)
{
	BYTE level1, level2, offset;
	// Decide which FIFO we are looking at
	N_UnlockAdditionalStatus();
	do{  // Read until two values the same
		if (fifo == RECEIVE_FIFO)
		{
			level1 = RFL_OFFSET&0x00ff;
			level2 = RFL_OFFSET&0x00ff;
		}	
		else
		{
			level1 = TFL_OFFSET&0x00ff;
			level2 = TFL_OFFSET&0x00ff;
		}	
	} while (level1 != level2);
	N_LockAdditionalStatus();

	return level1;
}

void N_SetPrescalerEnable (BOOL state)
{
	BYTE efr, mcr;
	// Store EFR and enable enhanced mode
	efr = N_Read650(EFR_OFFSET);
	N_Write650(EFR_OFFSET, efr | EFR_ENHANCED_MODE_EN);
	// Get current MCR value
	mcr = MCR_OFFSET;
	// Set the bit according to the state requested
	if (state)
		mcr |= MCR_PRESCALER_EN;
	else
		mcr &= ~MCR_PRESCALER_EN;
	//Write new value and restore EFR
	MCR_OFFSET = mcr;
	N_Write650(EFR_OFFSET, efr);
}

void N_Set950TriggerEnable(BOOL state)
{
	// Set the bit according to the state requested
	if (state)
		uart_dev.shadowACR |= ACR_950_TRIGGER_EN;
	else
		uart_dev.shadowACR &= ~ACR_950_TRIGGER_EN;
	//Write new value
	N_WriteICR(ACR_INDEX, uart_dev.shadowACR);
}

void N_SetReceiverEnable(BOOL state)
{
	// Set the bit according to the state requested
	if (state)
		uart_dev.shadowACR |= ACR_RX_DISABLE;
	else
		uart_dev.shadowACR &= ~ACR_RX_DISABLE;
	// Write new value
	N_WriteICR(ACR_INDEX, uart_dev.shadowACR);
}

void N_SetTransmitterEnable(BOOL state)
{
	// Set the bit according to the state requested
	if (state)
		uart_dev.shadowACR |= ACR_TX_DISABLE;
	else
		uart_dev.shadowACR &= ~ACR_TX_DISABLE;
	// Write new value
	N_WriteICR(ACR_INDEX, uart_dev.shadowACR);
}

void c950_init()
{     
	int i=0;
	
	
	//XINT1 used as configuration, XINT2 used as receiving data
	//Active at rising edge
	*IMR |= 0x0001;
	
	*XINT2CR = 0X8005;
	*XINT1CR = 0X8005;  
	
	uart_dev.shadowACR = 0x00;
	uart_dev.shadowFCR = 0x00;
	
	PortControl |= RESET_950;
	portA000=PortControl;
	for(i=0;i<100;i++)
	{
		i=i;
	}
	PortControl &= ~RESET_950;
	portA000=PortControl;

	// Initializing the UART	
    N_WriteICR(CSR_OFFSET, 0X00);	/*Writing 0x00 to CSR to reset the UART*/
    N_WriteDivisor (0x0001);	// DLL DLM
	LCR_OFFSET = LCR_MODE_8E1;	//line control register	
	N_Write650(EFR_OFFSET, EFR_ENHANCED_MODE_EN);
				/* 950 mode configuration is identical to 650 configuration*/
	MCR_OFFSET = 0x88;//ENABLE INT  Modem control register
	N_SetPrescalerEnable(TRUE);
	N_WriteICR(CPR_OFFSET, 0x08);//8Mbps
	N_WriteICR(TCR_OFFSET, 0x04);//8Mbps
	FCR_OFFSET = 0x01;			 //FIFO control register
//	FCR_OFFSET = 0x81;			 //FIFO control register	
	N_Set950TriggerEnable(TRUE);
	N_WriteICR(TTL_OFFSET, 127);
	N_WriteICR(RTL_OFFSET, 127);
	IER_OFFSET = 0x01; /* receiver data available, receiver status*/
						// Interrupt Enable Register
	uart_dev.isr_val = ISR_OFFSET;
	// record FCR
	uart_dev.shadowFCR = 0x01;
}

void SendOutData()
{
	int sendBuf[8];
	
	sendBuf[0] = (speedA & 0x00FF);
	sendBuf[1] = (speedA >> 8);
	
	sendBuf[2] = (speedB & 0x00FF);
	sendBuf[3] = (speedB >> 8);
	
	sendBuf[4] = (speedC & 0x00FF);
	sendBuf[5] = (speedC >> 8);
	
	sendBuf[6] = (speedD & 0x00FF);
	sendBuf[7] = (speedD >> 8);
	
	PortControl |= SEND_ENABLE;
	portA000 = PortControl;
	for(v_FIFOIdx = 0; v_FIFOIdx < v_FIFOCnts/2; v_FIFOIdx ++)
	{
		THR_OFFSET = sendBuf[v_FIFOIdx % 8];//v_RXFIFOBuf[v_FIFOIdx];
		//	THR_OFFSET = 0xaa;
	}
	do{
		
	}
	while(N_ReadFIFOLevel(TRANSMIT_FIFO)&0X00FF);
	
	PortControl &= ~SEND_ENABLE;
	portA000 = PortControl;
}