regdefine.h

CP2201和51单片机实现ARP ICMP IP UDP协议

/*--------------------------------------------------------------------------
REG51.H

Header file for generic 80C51 and 80C31 microcontroller.
Copyright (c) 1988-2002 Keil Elektronik GmbH and Keil Software, Inc.
All rights reserved.
--------------------------------------------------------------------------*/

/* the 51cpu is SST89v564RD */

#ifndef __REG51_H__
#define __REG51_H__

/*  BYTE Register  */
sfr P0   = 0x80;
sfr P1   = 0x90;
sfr P2   = 0xA0;
sfr P3   = 0xB0;
sfr PSW  = 0xD0;
sfr ACC  = 0xE0;
sfr B    = 0xF0;
sfr SP   = 0x81;
sfr DPL  = 0x82;
sfr DPH  = 0x83;
sfr PCON = 0x87;
sfr TCON = 0x88;
sfr TMOD = 0x89;
sfr TL0  = 0x8A;
sfr TL1  = 0x8B;
sfr TH0  = 0x8C;
sfr TH1  = 0x8D;
sfr IE   = 0xA8;
sfr IP   = 0xB8;
sfr SCON = 0x98;
sfr SBUF = 0x99;

/*added in sst89e564rd*/
sfr WDTD = 0x85;
sfr AUXR = 0x8e;
sfr AUXR1 = 0xa2;
sfr SADDR = 0xa9;
sfr SFCF = 0xb1;
sfr SFCM = 0xb2;
sfr SFAL = 0xb3;
sfr SFAH = 0xb4;
sfr SFDT = 0xb5;
sfr SFST = 0xb6;
sfr IPH  = 0xb7;
sfr SADEN = 0xb9;
sfr WDTC = 0xc0;
sfr T2CON = 0xc8;
sfr T2MOD = 0xc9;
sfr RCAP2L = 0xca;
sfr RCAP2H = 0xcb;
sfr TL2 = 0xcc;
sfr TH2 = 0xcd;
sfr CCON = 0xd8;
sfr CMOD = 0xd9;
sfr CCAPM0 = 0xda;
sfr CCAPM1 = 0xdb;
sfr CCAPM2 = 0xdc;
sfr CCAPM3 = 0xdd;
sfr CCAMP4 = 0xde;
sfr IEA = 0xe8;
sfr CL  = 0xe9;
sfr CCAP0L = 0xea;
sfr CCAP1L = 0xeb;
sfr CCAP2L = 0xec;
sfr CCAP3L = 0xed;
sfr CCAP4L = 0xee;

sfr IPAH = 0xf7;

sfr CH  = 0xf9;
sfr CCAP0H = 0xfa;
sfr CCAP1H = 0xfb;
sfr CCAP2H = 0xfc;
sfr CCAP3H = 0xfd;
sfr CCAP4H = 0xfe;

/*BIT Register,WDTC*/
sbit SWDT = WDTC^0;
sbit WDT  = WDTC^1;
sbit WDTS = WDTC^2;
sbit WDRE = WDTC^3;
sbit WDOUT = WDTC^4;
  
sbit RS1  = 0xD4;
/*  BIT Register  */
/*  PSW   */
sbit CY   = 0xD7;
sbit AC   = 0xD6;
sbit F0   = 0xD5;
sbit RS0  = 0xD3;
sbit OV   = 0xD2;
sbit P    = 0xD0;

/*  TCON  */
sbit TF1  = 0x8F;
sbit TR1  = 0x8E;
sbit TF0  = 0x8D;
sbit TR0  = 0x8C;
sbit IE1  = 0x8B;
sbit IT1  = 0x8A;
sbit IE0  = 0x89;
sbit IT0  = 0x88;

sbit TR2 = 0xCA;
sbit TF2 = 0xCF;
sbit EXF2 = 0xCE;
/*  IE   */
sbit EA   = 0xAF;
sbit ES   = 0xAC;
sbit ET1  = 0xAB;
sbit EX1  = 0xAA;
sbit ET0  = 0xA9;
sbit EX0  = 0xA8;
sbit ET2  = 0xAD; 

/*  IP   */ 
sbit PS   = 0xBC;
sbit PT1  = 0xBB;
sbit PX1  = 0xBA;
sbit PT0  = 0xB9;
sbit PX0  = 0xB8;

/*  P3  */
sbit RD   = 0xB7;
sbit WR   = 0xB6;
sbit T1   = 0xB5;
sbit T0   = 0xB4;
sbit INT1 = 0xB3;
sbit INT0 = 0xB2;
sbit TXD  = 0xB1;
sbit RXD  = 0xB0;

/*  SCON  */
sbit SM0  = 0x9F;
sbit SM1  = 0x9E;
sbit SM2  = 0x9D;
sbit REN  = 0x9C;
sbit TB8  = 0x9B;
sbit RB8  = 0x9A;
sbit TI   = 0x99;
sbit RI   = 0x98;

sbit NICRST = P1^0;  /* it comes from fpga */
sbit PWON_RST = P1^2;  /*reset exteral chip,0 is active, period 100ms-200ms,then 1*/
sbit RST = P1^7;  /* as the same as PWON_RST*/
//sbit INT = P3^2;  /*INT0*/????????????????????????????????????????????????????????????????????
sbit LM75_ALM = P3^3;  /*INT1,from netwok card*/
sbit SCL = P3^4;  /* 0 level is active*/
sbit SDA = P3^5;  /* 0 level is active*/
sbit FPGA_INTERRUPT = P3^2;  /* 0 level is active*/


#endif