📄 reg.h
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#ifndef _reg_h_
#define _reg_h_
#include <absacc.h>
//-----------------------------------------------------------------------------
// CP220x_REG.h
//-----------------------------------------------------------------------------
// Copyright 2006 Silicon Laboratories, Inc.
// http://www.silabs.com
//
// Program Description:
//
// Header File for CP220x Register Definitions.
//-----------------------------------------------------------------------------
// Indirect Register Definitions
//-----------------------------------------------------------------------------
#define MACCN 0x00 // MAC Control
#define MACCF 0x01 // MAC Configuration
#define IPGT 0x02 // Back-to-Back Interpacket Delay
#define IPGR 0x03 // Non-Back-to-Back Interpacket Delay
#define CWMAXR 0x04 // Collision Window and Maximum Retransmit
#define MAXLEN 0x05 // Maximum Frame Length
#define MACAD0 0x10 // MAC Address 0
#define MACAD1 0x11 // MAC Address 1
#define MACAD2 0x12 // MAC Address 2
//-----------------------------------------------------------------------------
// Direct Register Definitions
//-----------------------------------------------------------------------------
#define RAMADDRH XBYTE[0x8008] // RAM Address Pointer High Byte
#define RAMADDRL XBYTE[0x8009] // RAM Address Pointer Low Byte
#define RAMRXDATA XBYTE[0x8002] // RXFIFO RAM Data Register
#define RAMTXDATA XBYTE[0x8004] // TXBUFF RAM Data Register
#define FLASHADDRH XBYTE[0x8069] // Flash Address Pointer High Byte
#define FLASHADDRL XBYTE[0x8068] // Flash Address Pointer Low Byte
#define FLASHAUTORD XBYTE[0x8005] // Flash Autoread w/ increment
#define FLASHDATA XBYTE[0x8006] // Flash Read/Write Data Register
#define FLASHKEY XBYTE[0x8067] // Flash Lock and Key
#define FLASHERASE XBYTE[0x806A] // Flash Erase
#define FLASHSTA XBYTE[0x807B] // Flash Status
#define MACADDR XBYTE[0x800A] // MAC Address Pointer
#define MACDATAH XBYTE[0x800B] // MAC Data Register High Byte
#define MACDATAL XBYTE[0x800C] // MAC Data Register Low Byte
#define MACRW XBYTE[0x800D] // MAC Read/Write Initiate
#define INT0 XBYTE[0x8063] // Interrupt Status Register 0 (Self-Clearing)
#define INT0RD XBYTE[0x8076] // Interrupt Status Register 0 (Read-Only)
#define INT0EN XBYTE[0x8064] // Interrupt Enable Register 0
#define INT1 XBYTE[0x807F] // Interrupt Status Register 1 (Self-Clearing)
#define INT1RD XBYTE[0x807E] // Interrupt Status Register 1 (Read-Only)
#define INT1EN XBYTE[0x807D] // Interrupt Enable Register 1
#define VDMCN XBYTE[0x8013] // VDD Monitor Control Register
#define SWRST XBYTE[0x8075] // Software Reset Register
#define RSTSTA XBYTE[0x8073] // Reset Source Status Register
#define RSTEN XBYTE[0x8072] // Reset Enable Register
#define IOPWR XBYTE[0x8070] // Port Input/Output Power
#define OSCPWR XBYTE[0x807C] // Oscillator Power
#define RXFILT XBYTE[0x8010] // Receive Filter Configuraton
#define RXCN XBYTE[0x8011] // Receive Control
#define RXSTA XBYTE[0x8012] // Receive Status
#define RXAUTORD XBYTE[0x8001] // Receive Autoread w/ increment
#define RXHASHH XBYTE[0x800E] // Receive Hash Table High Byte
#define RXHASHL XBYTE[0x800F] // Receive Hash Table Low Byte
#define CPINFOH XBYTE[0x801D] // Current RX Packet Information High Byte
#define CPINFOL XBYTE[0x801E] // Current RX Packet Information Low Byte
#define CPLENH XBYTE[0x801F] // Current RX Packet Length High Byte
#define CPLENL XBYTE[0x8020] // Current RX Packet Length Low Byte
#define CPADDRH XBYTE[0x8021] // Current RX Packet Address High Byte
#define CPADDRL XBYTE[0x8022] // Current RX Packet Address Low Byte
#define CPTLB XBYTE[0x801A] // Current RX Packet TLB Number
#define TLBVALID XBYTE[0x801C] // TLB Valid Indicators
#define TLB0INFOH XBYTE[0x8023] // TLB0 Information High Byte
#define TLB0INFOL XBYTE[0x8024] // TLB0 Information Low Byte
#define TLB0LENH XBYTE[0x8025] // TLB0 Length High Byte
#define TLB0LENL XBYTE[0x8026] // TLB0 Length Low Byte
#define TLB0ADDRH XBYTE[0x8027] // TLB0 Address High Byte
#define TLB0ADDRL XBYTE[0x8028] // TLB0 Address Low Byte
#define TLB1INFOH XBYTE[0x8029] // TLB1 Information High Byte
#define TLB1INFOL XBYTE[0x802A] // TLB1 Information Low Byte
#define TLB1LENH XBYTE[0x802b] // TLB1 Length High Byte
#define TLB1LENL XBYTE[0x802C] // TLB1 Length Low Byte
#define TLB1ADDRH XBYTE[0x802D] // TLB1 Address High Byte
#define TLB1ADDRL XBYTE[0x802E] // TLB1 Address Low Byte
#define TLB2INFOH XBYTE[0x802F] // TLB2 Information High Byte
#define TLB2INFOL XBYTE[0x8030] // TLB2 Information Low Byte
#define TLB2LENH XBYTE[0x8031] // TLB2 Length High Byte
#define TLB2LENL XBYTE[0x8032] // TLB2 Length Low Byte
#define TLB2ADDRH XBYTE[0x8033] // TLB2 Address High Byte
#define TLB2ADDRL XBYTE[0x8034] // TLB2 Address Low Byte
#define TLB3INFOH XBYTE[0x8035] // TLB3 Information High Byte
#define TLB3INFOL XBYTE[0x8036] // TLB3 Information Low Byte
#define TLB3LENH XBYTE[0x8037] // TLB3 Length High Byte
#define TLB3LENL XBYTE[0x8038] // TLB3 Length Low Byte
#define TLB3ADDRH XBYTE[0x8039] // TLB3 Address High Byte
#define TLB3ADDRL XBYTE[0x803A] // TLB3 Address Low Byte
#define TLB4INFOH XBYTE[0x803B] // TLB4 Information High Byte
#define TLB4INFOL XBYTE[0x803C] // TLB4 Information Low Byte
#define TLB4LENH XBYTE[0x803D] // TLB4 Length High Byte
#define TLB4LENL XBYTE[0x803E] // TLB4 Length Low Byte
#define TLB4ADDRH XBYTE[0x803F] // TLB4 Address High Byte
#define TLB4ADDRL XBYTE[0x8040] // TLB4 Address Low Byte
#define TLB5INFOH XBYTE[0x8041] // TLB5 Information High Byte
#define TLB5INFOL XBYTE[0x8042] // TLB5 Information Low Byte
#define TLB5LENH XBYTE[0x8043] // TLB5 Length High Byte
#define TLB5LENL XBYTE[0x8044] // TLB5 Length Low Byte
#define TLB5ADDRH XBYTE[0x8045] // TLB5 Address High Byte
#define TLB5ADDRL XBYTE[0x8046] // TLB5 Address Low Byte
#define TLB6INFOH XBYTE[0x8047] // TLB6 Information High Byte
#define TLB6INFOL XBYTE[0x8048] // TLB6 Information Low Byte
#define TLB6LENH XBYTE[0x8049] // TLB6 Length High Byte
#define TLB6LENL XBYTE[0x804A] // TLB6 Length Low Byte
#define TLB6ADDRH XBYTE[0x804B] // TLB6 Address High Byte
#define TLB6ADDRL XBYTE[0x804C] // TLB6 Address Low Byte
#define TLB7INFOH XBYTE[0x804D] // TLB7 Information High Byte
#define TLB7INFOL XBYTE[0x804E] // TLB7 Information Low Byte
#define TLB7LENH XBYTE[0x804F] // TLB7 Length High Byte
#define TLB7LENL XBYTE[0x8050] // TLB7 Length Low Byte
#define TLB7ADDRH XBYTE[0x8051] // TLB7 Address High Byte
#define TLB7ADDRL XBYTE[0x8052] // TLB7 Address Low Byte
#define RXFIFOHEADH XBYTE[0x8017] // Receive Buffer Head Pointer High Byte
#define RXFIFOHEADL XBYTE[0x8018] // Receive Buffer Head Pointer Low Byte
#define RXFIFOTAILH XBYTE[0x8015] // Receive Buffer Tail Pointer High Byte
#define RXFIFOTAILL XBYTE[0x8016] // Receive Buffer Tail Pointer Low Byte
#define RXFIFOSTA XBYTE[0x805B] // Receive Buffer Status
#define TXSTARTH XBYTE[0x8059] // Transmit Data Starting Address High Byte
#define TXSTARTL XBYTE[0x805A] // Transmit Data Starting Address Low Byte
#define TXAUTOWR XBYTE[0x8003] // Transmit Data Autowrite
#define TXENDH XBYTE[0x8057] // Transmit Data Ending Address High Byte
#define TXENDL XBYTE[0x8058] // Transmit Data Ending Address Low Byte
#define TXCN XBYTE[0x8053] // Transmit Control
#define TXPAUSEH XBYTE[0x8055] // Transmit Pause High Byte
#define TXPAUSEL XBYTE[0x8056] // Transmit Pause Low Byte
#define TXBUSY XBYTE[0x8054] // Transmit Busy Indicator
#define TXSTA6 XBYTE[0x805C] // Transmit Status Vector 6
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