system_defbf561.h

自己写的adi bf561的bootloader.实现最简单的串口和flash

#define IMDMA_S0_CURR_X_COUNT 0xFFC01870 /*IMDMA Stream 0 Source Current Inner-Loop Count */
#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 /*IMDMA Stream 0 Source Current Outer-Loop Count */
#define IMDMA_S0_IRQ_STATUS 0xFFC01868 /*IMDMA Stream 0 Source Interrupt/Status */

#define IMDMA_D1_CONFIG 0xFFC01888 /*IMDMA Stream 1 Destination Configuration */
#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 /*IMDMA Stream 1 Destination Next Descriptor Ptr Reg */
#define IMDMA_D1_START_ADDR 0xFFC01884 /*IMDMA Stream 1 Destination Start Address */
#define IMDMA_D1_X_COUNT 0xFFC01890 /*IMDMA Stream 1 Destination Inner-Loop Count */
#define IMDMA_D1_Y_COUNT 0xFFC01898 /*IMDMA Stream 1 Destination Outer-Loop Count */
#define IMDMA_D1_X_MODIFY 0xFFC01894 /*IMDMA Stream 1 Dest Inner-Loop Address-Increment */
#define IMDMA_D1_Y_MODIFY 0xFFC0189C /*IMDMA Stream 1 Dest Outer-Loop Address-Increment */
#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 /*IMDMA Stream 1 Destination Current Descriptor Ptr */
#define IMDMA_D1_CURR_ADDR 0xFFC018A4 /*IMDMA Stream 1 Destination Current Address */
#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 /*IMDMA Stream 1 Destination Current Inner-Loop Count */
#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 /*IMDMA Stream 1 Destination Current Outer-Loop Count */
#define IMDMA_D1_IRQ_STATUS 0xFFC018A8 /*IMDMA Stream 1 Destination Interrupt/Status */

#define IMDMA_S1_CONFIG 0xFFC018C8 /*IMDMA Stream 1 Source Configuration */
#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 /*IMDMA Stream 1 Source Next Descriptor Ptr Reg */
#define IMDMA_S1_START_ADDR 0xFFC018C4 /*IMDMA Stream 1 Source Start Address */
#define IMDMA_S1_X_COUNT 0xFFC018D0 /*IMDMA Stream 1 Source Inner-Loop Count */
#define IMDMA_S1_Y_COUNT 0xFFC018D8 /*IMDMA Stream 1 Source Outer-Loop Count */
#define IMDMA_S1_X_MODIFY 0xFFC018D4 /*IMDMA Stream 1 Source Inner-Loop Address-Increment */
#define IMDMA_S1_Y_MODIFY 0xFFC018DC /*IMDMA Stream 1 Source Outer-Loop Address-Increment */
#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 /*IMDMA Stream 1 Source Current Descriptor Ptr reg */
#define IMDMA_S1_CURR_ADDR 0xFFC018E4 /*IMDMA Stream 1 Source Current Address */
#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 /*IMDMA Stream 1 Source Current Inner-Loop Count */
#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 /*IMDMA Stream 1 Source Current Outer-Loop Count */
#define IMDMA_S1_IRQ_STATUS 0xFFC018E8 /*IMDMA Stream 1 Source Interrupt/Status */



/*********************************************************************************** */
/* System MMR Register Bits */
/******************************************************************************* */

/* ********************* PLL AND RESET MASKS ************************ */

/*// PLL_CTL Masks */
#define PLL_CLKIN              0x00000000  /* Pass CLKIN to PLL */
#define PLL_CLKIN_DIV2         0x00000001  /* Pass CLKIN/2 to PLL */
#define PLL_OFF                0x00000002  /* Shut off PLL clocks */
#define STOPCK_OFF             0x00000008  /* Core clock off */
#define PDWN                   0x00000020  /* Put the PLL in a Deep Sleep state */
#define BYPASS                 0x00000100  /* Bypass the PLL */

/*// PLL_DIV Masks */

#define SCLK_DIV(x)  (x)		   /* SCLK = VCO / x */

#define CCLK_DIV1              0x00000000  /* CCLK = VCO / 1 */
#define CCLK_DIV2              0x00000010  /* CCLK = VCO / 2 */
#define CCLK_DIV4              0x00000020  /* CCLK = VCO / 4 */
#define CCLK_DIV8              0x00000030  /* CCLK = VCO / 8 */

/* SWRST Mask */
#define SYSTEM_RESET           0x00000007  /* Initiates a system software reset */
#define SWRST_DBL_FAULT_B      0x00000800  /* SWRST Core B Double Fault */
#define SWRST_DBL_FAULT_A      0x00001000  /* SWRST Core A Double Fault */
#define SWRST_WDT_B		       0x00002000  /* SWRST Watchdog B */
#define SWRST_WDT_A		       0x00004000  /* SWRST Watchdog A */
#define SWRST_OCCURRED         0x00008000  /* SWRST Status */


/* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */

/* SICu_IARv Masks	 */
/* u = A or B */
/* v = 0 to 7 */
/* w = 0 or 1 */

/* Per_number = 0 to 63 */
/* IVG_number = 7 to 15   */
#define Peripheral_IVG(Per_number, IVG_number)    \
				( (IVG_number) -7) << ( ((Per_number)%8) *4) 	   /* Peripheral #Per_number assigned IVG #IVG_number  */
																   /* Usage: r0.l = lo(Peripheral_IVG(62, 10)); */
																   /*        r0.h = hi(Peripheral_IVG(62, 10)); */

 

/* SICx_IMASKw Masks */
/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers  */
#define SIC_UNMASK_ALL         0x00000000  /* Unmask all peripheral interrupts */
#define SIC_MASK_ALL           0xFFFFFFFF  /* Mask all peripheral interrupts */
#define SIC_MASK(x)	       (1 << (x))    /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */

/* SIC_IWR Masks */
#define IWR_DISABLE_ALL        0x00000000  /* Wakeup Disable all peripherals */
#define IWR_ENABLE_ALL         0xFFFFFFFF  /* Wakeup Enable all peripherals */
/* x = pos 0 to 31, for 32-63 use value-32 */
#define IWR_ENABLE(x)	       (1 << (x))    /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */



/* ********* WATCHDOG TIMER MASKS ******************** */
  
/* Watchdog Timer WDOG_CTL Register Masks */
  
#define WDEV(x) ((x<<1) & 0x0006) /* event generated on roll over */
#define WDEV_RESET 0x0000 /* generate reset event on roll over */
#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
#define WDEV_NONE 0x0006 /* no event on roll over */
#define WDEN 0x0FF0 /* enable watchdog */
#define WDDIS 0x0AD0 /* disable watchdog */
#define WDRO 0x8000 /* watchdog rolled over latch */ 

/* depreciated WDOG_CTL Register Masks for legacy code */


#define ICTL WDEV
#define ENABLE_RESET WDEV_RESET
#define WDOG_RESET WDEV_RESET
#define ENABLE_NMI WDEV_NMI
#define WDOG_NMI WDEV_NMI
#define ENABLE_GPI WDEV_GPI
#define WDOG_GPI WDEV_GPI
#define DISABLE_EVT WDEV_NONE
#define WDOG_NONE WDEV_NONE

#define TMR_EN WDEN
#define TMR_DIS WDDIS
#define TRO WDRO



/* ***************************** UART CONTROLLER MASKS ********************** */

/* UART_LCR Register */

#define DLAB	0x80
#define SB      0x40
#define STP      0x20
#define EPS     0x10
#define PEN	0x08
#define STB	0x04
#define WLS(x)	((x-5) & 0x03)

#define DLAB_P	0x07
#define SB_P	0x06
#define STP_P	0x05
#define EPS_P	0x04
#define PEN_P	0x03
#define STB_P	0x02
#define WLS_P1	0x01
#define WLS_P0	0x00

/* UART_MCR Register */
#define LOOP_ENA	0x10
#define LOOP_ENA_P	0x04

/* UART_LSR Register */
#define TEMT	0x40
#define THRE	0x20
#define BI	0x10
#define FE	0x08
#define PE	0x04
#define OE	0x02
#define DR	0x01

#define TEMP_P	0x06
#define THRE_P	0x05
#define BI_P	0x04
#define FE_P	0x03
#define PE_P	0x02
#define OE_P	0x01
#define DR_P	0x00

/* UART_IER Register */
#define ELSI	0x04
#define ETBEI	0x02
#define ERBFI	0x01

#define ELSI_P	0x02
#define ETBEI_P	0x01
#define ERBFI_P	0x00

/* UART_IIR Register */
#define STATUS(x)	((x << 1) & 0x06)
#define NINT		0x01
#define STATUS_P1	0x02
#define STATUS_P0	0x01
#define NINT_P		0x00

/* UART_GCTL Register */
#define FFE	0x20
#define FPE	0x10
#define RPOLC	0x08
#define TPOLC	0x04
#define IREN	0x02
#define UCEN	0x01

#define FFE_P	0x05
#define FPE_P	0x04
#define RPOLC_P	0x03
#define TPOLC_P	0x02
#define IREN_P	0x01
#define UCEN_P	0x00

/* **********  SERIAL PORT MASKS  ************