su164fsh.a66

LIN_InitNode_C161xx.h preconfiguration for C161xx LIN_InitNode_C164xx.h preconfiguration for C164

$MOD167					; Define C167 mode
;
;------------------------------------------------------------------------------
;  This file is part of the C166 Compiler package
;  Copyright KEIL ELEKTRONIK GmbH 1996
;------------------------------------------------------------------------------
;  START167.A66:  This code is executed after processor reset and provides
;                 the startup sequence for the C167/C165/C163 processor.
;
;  To translate this file use A166 with the following invocation:
;
;     A166 START167.A66 SET (<model>)
;
;     <model> determines the memory model and can be one of the following:
;         TINY, SMALL, COMPACT, HCOMPACT, MEDIUM, LARGE or HLARGE
;
;  Example:  A166 START167.A66 SET (SMALL)
;
;  To link the modified START167.OBJ file to your application use the following
;  L166 invocation:
;
;     L166 <your object file list>, START167.OBJ <controls>
;
;------------------------------------------------------------------------------
; Setup model-dependend Assembler controls
$CASE
$IF NOT TINY
$SEGMENTED
$ENDIF
;------------------------------------------------------------------------------
;
; Definitions for SYSCON and BUSCON0 Register:
; --------------------------------------------
;
; MCTC0: Memory Cycle Time (BUSCON0.0 .. BUSCON0.3):
; Note: if RDYEN0 == 1 a maximum number of 7 waitstates can be selected
_MCTC0	 EQU	1	; Memory wait states is 1 (MCTC0 field = 0EH).
;			; (Reset Value = 15 additional state times)
;
; RWDC0: Read/Write Signal Delay (BUSCON0.4):
_RWDC0	 EQU	0	; 0 = Delay Time     0.5 States (Reset Value)  
;			; 1 = No Delay Time  0   States
;
; MTTC0: Memory Tri-state Time (BUSCON0.5):
_MTTC0	 EQU	1	; 0 = Delay Time     0.5 States (Reset Value)
;			; 1 = No Delay Time  0   States
;
$SET (BTYP_ENABLE = 0)  ; 0 = BTYP0 and BUSACT0 is set according to the level
                        ;     at pins P0L.6 and P0L.7 during reset.
			; 1 = the following _BTYP0 and _BUSACT0 values are
			;     written to BTYP0 and BUSACT0
;
; BTYP0: External Bus Configuration Control (BUSCON0.6 .. BUSCON0.7):
_BTYP0	 EQU	3	; 0 = 8 Bit Non Multiplexed
;			; 1 = 8 Bit Multiplexed
;			; 2 = 16 Bit Non Multiplexed
;			; 3 = 16 Bit Multiplexed
;
; ALECTL0: ALE Lengthening Control Bit (BUSCON0.9):
_ALECTL0 EQU	0	; see data sheet for description
;
; BUSACT0: Bus Active Control Bit (BUSCON0.10):
_BUSACT0 EQU	1	; = 0 external bus disabled
			; = 1 external bus enabled
;
; RDYEN0: READY# Input Enable control bit (BUSCON0.12):
_RDYEN0  EQU	0	; 0 = READY# function disabled  (Reset Value)
;			; 1 = READY# function enabled
;
; RDY_AS: Synchronous / Asynchronous READY# Input (BUSCON.3):
; Note: This bit is only valid if _RDYEN == 1.
_RDY_AS EQU	0	; 0 = synchronous READY# input
;			; 1 = asynchronous READY# input
;
; XRAMEN: XRAM Enable Control Bit (SYSCON.2)
_XRAMEN	EQU	1	; 0 = access to on-chip XRAM disable, ext. bus access
;                       ; 1 = on-chip XRAM is accessed
;
; WRCFG: Write Configuration Control Bit (SYSCON.7):
_WRCFG	 EQU	0	; 0 = Normal configuration of WR# and BHE#
;			; 1 = WR# pin acts as WRL#, BHE# pin acts as WRH#
;
; CLKEN: System Clock Output Enable bit (SYSCON.8):
_CLKEN	EQU	1	; 0 = disabled    (Reset Value)
;			; 1 = enabled
;
; BYTDIS: Byte High Enable pin control bit (SYSCON.9):
_BYTDIS	EQU	0	; 0 = enabled     (Reset Value)
;			; 1 = disabled
;
; ROMEN: Internal ROM Access Enable is read only (SYSCON.10):
_ROMEN	EQU	1	; 0 = Internal ROM disabled
			; 1 = Internal ROM enabled
;
; SGTDIS: Segmentation Disable control bit (SYSCON.11):
$IF TINY
_SGTDIS	EQU	1	; disable segmented mode for TINY model
$ELSE
_SGTDIS	EQU	0	; enable segmented mode (Reset Value)
$ENDIF
;
; ROMS1: ROM Segment Mapping Control Bit (SYSCON.12):
_ROMS1  EQU	0	; _ROMS1 = 0 Internal ROM mapped to segment 0
;			; _ROMS1 = 1 Internal ROM mapped to segment 1
;
; STKSZ: Maximum System Stack Size selection  (SYSCON.13 .. SYSCON.15)
;  Defines the system stack space which is used by CALL/RET and PUSH/POP
;  instructions.  The system stack space must be adjusted according the
;  actual requirements of the application.
$SET (STK_SIZE = 1)
;     System stack sizes:
;       0 = 256 words (Reset Value)
;       1 = 128 words
;       2 =  64 words
;       3 =  32 words
;       4 = 512 words
;       5 = not implemented
;       6 = not implemented
;       7 = no wrapping (entire internal RAM use as STACK, set size with SYSSZ)
; If you have selected 7 for STK_SIZE, you can set the actual system stack size
; with the following SSTSZ statement.
SSTSZ	EQU	200H	; set System Stack Size to 200H Bytes
;
; USTSZ: User Stack Size Definition 
;  Defines the user stack space available for automatics.  This stack space is
;  accessed by R0.  The user stack space must be adjusted according the actual
;  requirements of the application.
USTSZ	EQU	400H	; set User Stack Size to 1000H Bytes.
;
; WATCHDOG: Disable Hardware Watchdog
; --- Set WATCHDOG = 1 to enable the Hardware watchdog
$SET (WATCHDOG = 0)
;
;
; CLR_MEMORY: Disable Memory Zero Initialization of RAM area
; --- Set CLR_MEMORY = 0 to disable memory zero initilization
$SET (CLR_MEMORY = 1)
;
; INIT_VARS: Disable Variable Initialization
; --- Set INIT_VARS = 0 to disable variable initilization
$SET (INIT_VARS = 1)
;
; DPPUSE:  Re-assign DPP registers
; --- Set DPPUSE = 0 to reduce the code size of the startup code, if you
;                    are not using the L166 DPPUSE directive.
$SET (DPPUSE = 1)
;
;------------------------------------------------------------------------------
;
; BUSCON1/ADDRSEL1 .. BUSCON4/ADDRSEL4 Initialization
; ===================================================
;
;
; BUSCON1/ADDRSEL1
; --- Set BUSCON1 = 1 to initialize the BUSCON1/ADDRSEL1 registers
$SET (BUSCON1 = 0)
;
; Define the start address and the address range of Chip Select 1 (CS1#) 
; This values are used to set the ADDRSEL1 register
%DEFINE (ADDRESS1) (100000H)     ; Set CS1# Start Address (default 100000H)
%DEFINE (RANGE1)   (1024K)       ; Set CS1# Range (default 1024K = 1MB)
;  
; MCTC1: Memory Cycle Time (BUSCON1.0 .. BUSCON1.3):
; Note: if RDYEN1 == 1 a maximum number of 7 waitstates can be selected
_MCTC1	 EQU	1	; Memory wait states is 1 (MCTC1 field = 0EH).
;
; RWDC1: Read/Write Signal Delay (BUSCON1.4):
_RWDC1	 EQU	0	; 0 = Delay Time     0.5 States
;			; 1 = No Delay Time  0   States
;
; MTTC1: Memory Tri-state Time (BUSCON1.5):
_MTTC1	 EQU	1	; 0 = Delay Time     0.5 States
;			; 1 = No Delay Time  0   States
;
; BTYP1: External Bus Configuration Control (BUSCON1.6 .. BUSCON1.7):
_BTYP1	 EQU	2	; 0 = 8 Bit Non Multiplexed
;			; 1 = 8 Bit Multiplexed
;			; 2 = 16 Bit Non Multiplexed
;			; 3 = 16 Bit Multiplexed
;
; ALECTL1: ALE Lengthening Control Bit (BUSCON1.9):
_ALECTL1 EQU	0	; see data sheet for description
;
; BUSACT1: Bus Active Control Bit (BUSCON1.10):
_BUSACT1 EQU	1	; = 0 external (ADDRSEL1) bus disabled
			; = 1 external (ADDRSEL1) bus enabled
;
; RDYEN1: READY# Input Enable control bit (BUSCON1.12):
_RDYEN1  EQU	0	; 0 = READY# function disabled
;			; 1 = READY# function enabled
;
; CSREN1: Read Chip Select Enable bit (BUSCON1.14):
_CSREN1  EQU	0	; 0 = CS1# is independent of read command (RD#)
;			; 1 = CS1# is generated for the duration of read
;
; CSWEN1: Read Chip Select Enable bit (BUSCON1.15):
_CSWEN1  EQU	0	; 0 = CS1# is independent of write command (RD#)
;			; 1 = CS1# is generated for the duration of write
;
;
; BUSCON2/ADDRSEL2
; --- Set BUSCON2 = 1 to initialize the BUSCON2/ADDRSEL2 registers
$SET (BUSCON2 = 0)
;
; Define the start address and the address range of Chip Select 2 (CS2#) 
; This values are used to set the ADDRSEL2 register
%DEFINE (ADDRESS2) (200000H)     ; Set CS2# Start Address (default 200000H)
%DEFINE (RANGE2)   (1024K)       ; Set CS2# Range (default 1024K = 1MB)
;  
; MCTC2: Memory Cycle Time (BUSCON2.0 .. BUSCON2.3):
; Note: if RDYEN2 == 1 a maximum number of 7 waitstates can be selected
_MCTC2	 EQU	1	; Memory wait states is 1 (MCTC2 field = 0EH).
;
; RWDC2: Read/Write Signal Delay (BUSCON2.4):
_RWDC2	 EQU	0	; 0 = Delay Time     0.5 States
;			; 1 = No Delay Time  0   States
;
; MTTC2: Memory Tri-state Time (BUSCON2.5):
_MTTC2	 EQU	1	; 0 = Delay Time     0.5 States
;			; 1 = No Delay Time  0   States
;
; BTYP2: External Bus Configuration Control (BUSCON2.6 .. BUSCON2.7):
_BTYP2	 EQU	2	; 0 = 8 Bit Non Multiplexed
;			; 1 = 8 Bit Multiplexed
;			; 2 = 16 Bit Non Multiplexed
;			; 3 = 16 Bit Multiplexed
;
; ALECTL2: ALE Lengthening Control Bit (BUSCON2.9):
_ALECTL2 EQU	0	; see data sheet for description
;
; BUSACT2: Bus Active Control Bit (BUSCON2.10):
_BUSACT2 EQU	1	; = 0 external (ADDRSEL2) bus disabled
			; = 1 external (ADDRSEL2) bus enabled
;
; RDYEN2: READY# Input Enable control bit (BUSCON2.12):
_RDYEN2  EQU	0	; 0 = READY# function disabled
;			; 1 = READY# function enabled
;
; CSREN2: Read Chip Select Enable bit (BUSCON2.14):
_CSREN2  EQU	0	; 0 = CS2# is independent of read command (RD#)
;			; 1 = CS2# is generated for the duration of read
;
; CSWEN2: Read Chip Select Enable bit (BUSCON2.15):
_CSWEN2  EQU	0	; 0 = CS2# is independent of write command (RD#)
;			; 1 = CS2# is generated for the duration of write
;
;
; BUSCON3/ADDRSEL3
; --- Set BUSCON3 = 1 to initialize the BUSCON3/ADDRSEL3 registers
$SET (BUSCON3 = 0)
;
; Define the start address and the address range of Chip Select 3 (CS3#) 
; This values are used to set the ADDRSEL3 register
%DEFINE (ADDRESS3) (300000H)     ; Set CS3# Start Address (default 300000H)
%DEFINE (RANGE3)   (1024K)       ; Set CS3# Range (default 1024K = 1MB)
;  
; MCTC3: Memory Cycle Time (BUSCON3.0 .. BUSCON3.3):
; Note: if RDYEN3 == 1 a maximum number of 7 waitstates can be selected
_MCTC3	 EQU	1	; Memory wait states is 1 (MCTC3 field = 0EH).
;
; RWDC3: Read/Write Signal Delay (BUSCON3.4):
_RWDC3	 EQU	0	; 0 = Delay Time     0.5 States
;			; 1 = No Delay Time  0   States
;
; MTTC3: Memory Tri-state Time (BUSCON3.5):
_MTTC3	 EQU	1	; 0 = Delay Time     0.5 States
;			; 1 = No Delay Time  0   States
;
; BTYP3: External Bus Configuration Control (BUSCON3.6 .. BUSCON3.7):
_BTYP3	 EQU	2	; 0 = 8 Bit Non Multiplexed
;			; 1 = 8 Bit Multiplexed
;			; 2 = 16 Bit Non Multiplexed
;			; 3 = 16 Bit Multiplexed
;
; ALECTL3: ALE Lengthening Control Bit (BUSCON3.9):
_ALECTL3 EQU	0	; see data sheet for description
;
; BUSACT3: Bus Active Control Bit (BUSCON3.10):
_BUSACT3 EQU	1	; = 0 external (ADDRSEL3) bus disabled
			; = 1 external (ADDRSEL3) bus enabled
;
; RDYEN3: READY# Input Enable control bit (BUSCON3.12):
_RDYEN3  EQU	0	; 0 = READY# function disabled
;			; 1 = READY# function enabled
;
; CSREN3: Read Chip Select Enable bit (BUSCON3.14):
_CSREN3  EQU	0	; 0 = CS3# is independent of read command (RD#)
;			; 1 = CS3# is generated for the duration of read
;
; CSWEN3: Read Chip Select Enable bit (BUSCON3.15):
_CSWEN3  EQU	0	; 0 = CS3# is independent of write command (RD#)
;			; 1 = CS3# is generated for the duration of write
;
;
; BUSCON4/ADDRSEL4
; --- Set BUSCON4 = 1 to initialize the BUSCON4/ADDRSEL4 registers
$SET (BUSCON4 = 0)
;
; Define the start address and the address range of Chip Select 4 (CS4#) 
; This values are used to set the ADDRSEL4 register
%DEFINE (ADDRESS4) (400000H)     ; Set CS4# Start Address (default 400000H)
%DEFINE (RANGE4)   (1024K)       ; Set CS4# Range (default 1024K = 1MB)
;  
; MCTC4: Memory Cycle Time (BUSCON4.0 .. BUSCON4.3):
; Note: if RDYEN4 == 1 a maximum number of 7 waitstates can be selected
_MCTC4	 EQU	1	; Memory wait states is 1 (MCTC4 field = 0EH).
;
; RWDC4: Read/Write Signal Delay (BUSCON4.4):
_RWDC4	 EQU	0	; 0 = Delay Time     0.5 States
;			; 1 = No Delay Time  0   States
;
; MTTC4: Memory Tri-state Time (BUSCON4.5):
_MTTC4	 EQU	1	; 0 = Delay Time     0.5 States
;			; 1 = No Delay Time  0   States
;
; BTYP4: External Bus Configuration Control (BUSCON4.6 .. BUSCON4.7):
_BTYP4	 EQU	2	; 0 = 8 Bit Non Multiplexed
;			; 1 = 8 Bit Multiplexed
;			; 2 = 16 Bit Non Multiplexed
;			; 3 = 16 Bit Multiplexed
;
; ALECTL4: ALE Lengthening Control Bit (BUSCON4.9):
_ALECTL4 EQU	0	; see data sheet for description
;
; BUSACT4: Bus Active Control Bit (BUSCON4.10):
_BUSACT4 EQU	1	; = 0 external (ADDRSEL4) bus disabled
			; = 1 external (ADDRSEL4) bus enabled
;
; RDYEN4: READY# Input Enable control bit (BUSCON4.12):
_RDYEN4  EQU	0	; 0 = READY# function disabled
;			; 1 = READY# function enabled
;
; CSREN4: Read Chip Select Enable bit (BUSCON4.14):
_CSREN4  EQU	0	; 0 = CS4# is independent of read command (RD#)
;			; 1 = CS4# is generated for the duration of read
;
; CSWEN4: Read Chip Select Enable bit (BUSCON4.15):
_CSWEN4  EQU	0	; 0 = CS4# is independent of write command (RD#)
;			; 1 = CS4# is generated for the duration of write
;
;------------------------------------------------------------------------------

$IF TINY
$SET (DPPUSE = 0)
$ENDIF

_STKSZ		SET	0
_STKSZ1		SET	0		; size is 512 Words
$IF (STK_SIZE = 0)
_STKSZ1		SET	1		; size is 256 Words
$ENDIF
$IF (STK_SIZE = 1)
_STKSZ		SET	1
_STKSZ1		SET	2		; size is 128 Words
$ENDIF
$IF (STK_SIZE = 2)
_STKSZ		SET	2
_STKSZ1		SET	3		; size is  64 Words
$ENDIF
$IF (STK_SIZE = 3)
_STKSZ		SET	3
_STKSZ1		SET	4		; size is  32 Words
$ENDIF
$IF (STK_SIZE = 4)
_STKSZ		SET	4
$ENDIF
$IF (STK_SIZE = 5)
_STKSZ		SET	5
$ENDIF
$IF (STK_SIZE = 6)
_STKSZ		SET	6
$ENDIF
$IF (STK_SIZE = 7)
_STKSZ		SET	7
$ENDIF


$IF NOT TINY
ASSUME	DPP3:SYSTEM
ASSUME  DPP2:NDATA
$ENDIF

NAME	?C_STARTUP
PUBLIC	?C_STARTUP

$IF MEDIUM OR LARGE OR HLARGE
Model	LIT	'FAR'
$ELSE
Model	LIT	'NEAR'
$ENDIF

EXTRN	main:Model

PUBLIC		?C_USRSTKBOT

?C_USERSTACK	SECTION	DATA PUBLIC 'NDATA'
$IF NOT TINY
NDATA		DGROUP	?C_USERSTACK
$ENDIF
?C_USRSTKBOT:
		DS	USTSZ		; Size of User Stack
?C_USERSTKTOP:
?C_USERSTACK	ENDS

?C_MAINREGISTERS	REGDEF	R0 - R15

$IF (STK_SIZE = 7)

?C_SYSSTACK	SECTION	DATA PUBLIC 'IDATA'
$IF NOT TINY
SDATA		DGROUP	?C_SYSSTACK
$ENDIF
_BOS:					; bottom of system stack
		DS	SSTSZ		; Size of User Stack
_TOS:					; top of system stack
?C_SYSSTACK	ENDS

$ELSE
; Setup Stack Overflow
_TOS	EQU	0FC00H			        ; top of system stack
_BOS	EQU	_TOS - (1024 >> _STKSZ1)	; bottom of system stack
$ENDIF

PUBLIC		?C_SYSSTKBOT
?C_SYSSTKBOT	EQU	_BOS

		SSKDEF	_STKSZ		; System stack size

?C_STARTUP_CODE	SECTION	CODE	'ICODE'