read.me

软件包 ucosii 在 z80 机器上的遗址

                         uC/OS-II, The Real-Time Kernel

                                Zilog Z-80 Port
                        
                                 READ ME FILE


------------------------------- IAR C COMPILER --------------------------------
1) The  current  version  of  the port is based on the IAR C Compiler V4.05 and
   the C-Spy Instruction Set Simulator (ISS) version 2.31B:

    IAR Systems Software, Inc.
    One Maritime Plaza, Suite 1770
    San Francisco, CA 94111
    USA
    
    415-765-5500
    415-765-5503 (FAX)
    
    www.iar.com
    [e-mail]
    
2) The C compiler and assembler are assumed to reside  in the C:\IAR\EW23\Z80\BIN 
   directory.

3) The code was tested using the  IAR C-Spy V2.31B Windows  based Instruction Set
   Simulator (ISS) and was not tested on actual hardware.  You will need to provide
   a 'tcik interrupt' source which needs to vector to OSTickISR() in ISR.ASM.

4) The C-Spy debugger is assumed to reside in the C:\IAR\EW23 directory.


----------------------------------- PORT NOTES --------------------------------

1) The port installation batch file (INSTALL.BAT) places the Z-80 port is the 
   following directory of the selected drive:
   
   \SOFTWARE\uCOS-II\Z-Z80\IAR
   
   This directory contains the following sub-directories:
   
   \SOFTWARE\uCOS-II\Z-Z80\IAR\SOURCE
       This directory contains the port source files: OS_CPU_A.ASM, OS_CPU_C.C
       and OS_CPU.H
   
   \SOFTWARE\uCOS-II\Z-Z80\IAR\TEST
       This directory contains the following source code file:
           INCLUDES.H
           This is a MASTER header include file that all uC/OS-II files expect.
           
           ISR.ASM
           This file contains the RESTART vector table.  RST 20H is used by the
           task level context switch function (OSCtxSw()).  If you need to use
           RST 20H for something else, make sure that you correctly assign the 
           new RESTART vector in OS_CPU.H and recompile the code.
           ISR.ASM also contains the interrupt vector table OSIntVectorTbl[].  
           For uC/OS-II, Timer #0 is used for the tick handler.  Other vectors 
           should be placed in this table.
           ISRs MUST be written in assembly language.  To help you do this, I 
           also included a 'template' (see YourISR in ISR.ASM).
           
           OS_CFG.H
           This file configures the services of uC/OS-II.
           
           TEST.C
           This contains sample test code which shows how to properly start a
           uC/OS-II application.
           
           TEST.XCL
           This file is an IAR linker command file.  It is assumed that Z-80
           memory map is as follows:
               CODE  0x0000 - 0x7FFF  (32K)
               RAM   0x8000 - 0xFFFF  (32K)

           uCOS_II.C
           This is a MASTER include file that is used to compile ALL of uC/OS-II's
           modules (OS_CPU_C.C, OS_CORE.C, OS_MBOX.C, OS_MEM.C, OS_Q.C, OS_SEM.C,
           OS_TASK.C, OS_TIME.C) with a single .C file.
           
       This directory also contains the build files to build the example code:
           MAKETEST.BAT
           TEST.MAK
       
   \SOFTWARE\uCOS-II\Z-Z80\IAR\WORK
       This is the directory in which the test code is built from.
       
   \SOFTWARE\uCOS-II\Z-Z80\IAR\OBJ
       This  directory  contains the  object files produced by the compiler and
       assembler.
       
   \SOFTWARE\uCOS-II\Z-Z80\IAR\LST
       This directory contains the 'listing' files produced by the compiler and
       the assembler.  For the C compiler, these files contain the  interleaved
       C source along with the assembly language code generated by the compiler.
   
2) The port was not tested with actual hardware, only the C-Spy Instruction Set
   Simulator.  However, it is believed to be correct.

3) The 'RST 20H' instruction is used by uC/OS-II for task level context switching.
   The 'RST 20H' vectors to absolute address 0x0020 where a jump instruction 
   (JP OSCtxSw) is inserted to jump to 'OSCtxSw()' (see OS_CPU_A.ASM).  
   OS_TASK_SW() uses the IAR compiler intrinsic function _opc(0xE7) which defines
   the opcode for the RST 20H (also known as RST 32).

4) You need to have a time base source generate an interrupt for the clock tick.  
   The timer interrupt vector needs to be placed in ISR.ASM and point to OSTickISR() 
   (see ISR.ASM).  
   
5) ISRs MUST be written in assembly language.  You can edit ISR.ASM and add your 
   own ISRs.  If your ISR needs to perform some functions in C then you should 
   invoke your C handler by placing the following code:
   
        CALL    YourISRHandler             ; Call YOUR interrupt handler in C         
 
6) All the registers are saved during a context switch.
   
7) It is expected that you will enable interrupts in the FIRST task that runs
   under uC/OS-II (see TEST.C for an example).
   
8) If you were using uC/OS's data types (BYTE, UBYTE, WORD, UWORD etc.) you will
   NOT need to change those.  However, it's recommended that you use the new data
   types: INT8S, INT8U, INT16S, INT16U etc.).   
   


------------------------------ REPORTING PROBLEMS -----------------------------

If  you find a problem (i.e. bug) in uC/OS-II or this port,  do not hesitate to
report the problem to me:

 1) Through the INTERNET:

        My INTERNET address is:   [e-mail]

 2) By writing to me:

        Micrium, Inc.
        c/o Jean J. Labrosse
        949 Crestview Circle
        Weston, FL 33327
        U.S.A.

 3) By calling me:

        [phone]
        [phone]   (FAX)

 4) By consulting the web sites:

        www.Micrium.com
              or
        www.uCOS-II.com

Make sure that the problem you are  reporting is in  uC/OS-II or this port and
not your application.    

---------------------------------- RELEASE NOTES -----------------------------

June 20, 2000: V1.01
--------------------

 1) Modified the context switch and stack initialization code to save all the CPU
    registers (i.e. the main and alternate registers).
    

May 12, 2000: V1.00
-------------------

 1) First release of the Z-Z80 port.