📄 dianti.rpt
字号:
- 5 - A 04 OR2 s 1 1 0 6 ~5411~10
- 2 - A 12 OR2 s 1 2 0 2 ~5411~11
- 2 - B 20 OR2 s 0 2 0 7 ~5435~1
- 3 - A 22 OR2 s 1 3 0 1 ~5435~2
- 7 - C 20 OR2 s 1 3 0 1 ~5459~1
- 5 - A 22 OR2 s 4 0 0 2 ~5483~1
- 4 - A 22 OR2 s 2 2 0 1 ~5495~1
- 7 - A 22 OR2 s 4 0 0 1 ~5495~2
- 5 - C 18 OR2 s 3 0 0 1 ~5507~1
- 5 - A 11 AND2 s 2 1 0 1 ~5531~1
- 6 - A 11 OR2 s 0 4 0 1 ~5531~2
- 3 - A 06 OR2 s 0 3 0 1 ~5531~3
- 7 - A 11 AND2 s 1 2 0 1 ~5531~4
- 8 - A 06 OR2 s 0 4 0 1 ~5531~5
- 2 - A 11 OR2 s 1 3 0 1 ~5531~6
- 6 - A 18 OR2 s 0 3 0 1 ~5531~7
- 7 - A 18 OR2 s 1 3 0 1 ~5531~8
- 8 - A 18 OR2 s 1 3 0 1 ~5531~9
- 1 - A 20 OR2 s 1 2 0 2 ~5543~1
- 1 - B 15 OR2 0 4 0 1 :5561
- 4 - B 16 OR2 s 2 2 0 1 ~5591~1
- 6 - B 16 OR2 s 1 3 0 1 ~5591~2
- 5 - B 22 OR2 s 1 3 0 3 ~5603~1
- 6 - B 22 OR2 s 1 2 0 1 ~5603~2
- 7 - B 22 OR2 s 0 4 0 1 ~5603~3
- 4 - B 17 OR2 s ! 2 0 0 21 ~5617~1
- 3 - B 22 AND2 s 1 2 0 3 ~5617~2
- 4 - B 22 AND2 s 1 3 0 1 ~5617~3
- 5 - B 20 OR2 s 0 4 0 1 ~5629~1
- 6 - B 20 AND2 s 0 2 0 1 ~5629~2
- 5 - B 16 OR2 s 0 4 0 3 ~5641~1
- 7 - B 20 OR2 s 1 2 0 1 ~5641~2
- 8 - B 20 AND2 s 0 3 0 1 ~5641~3
- 3 - B 16 OR2 s 0 2 0 1 ~5641~4
- 3 - B 15 AND2 s 1 2 0 2 ~5653~1
- 5 - B 21 AND2 s ! 0 4 0 2 ~5653~2
- 6 - B 21 OR2 s 0 4 0 1 ~5653~3
- 7 - B 21 AND2 s 0 3 0 1 ~5653~4
- 3 - B 17 OR2 s 1 1 0 7 ~5665~1
- 5 - B 18 OR2 s 0 3 0 1 ~5665~2
- 7 - B 18 OR2 s 0 4 0 1 ~5665~3
- 2 - B 21 AND2 s 0 3 0 1 ~5665~4
- 3 - B 21 AND2 s 0 3 0 1 ~5665~5
- 1 - B 18 OR2 s 0 2 0 2 ~5677~1
- 2 - B 18 OR2 s 0 4 0 1 ~5677~2
- 4 - B 18 OR2 s 0 4 0 1 ~5677~3
- 2 - B 16 AND2 s ! 0 2 0 3 ~5689~1
- 8 - B 16 OR2 s 1 1 0 6 ~5689~2
- 3 - B 18 OR2 s 0 3 0 2 ~5689~3
- 7 - B 17 AND2 s 0 3 0 1 ~5689~4
- 8 - B 17 OR2 s 0 3 0 1 ~5689~5
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\a\dianti.rpt
dianti
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 40/ 96( 41%) 31/ 48( 64%) 24/ 48( 50%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
B: 9/ 96( 9%) 0/ 48( 0%) 28/ 48( 58%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
C: 4/ 96( 4%) 0/ 48( 0%) 13/ 48( 27%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\a\dianti.rpt
dianti
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 84 clk
Device-Specific Information: e:\a\dianti.rpt
dianti
** EQUATIONS **
c_d2 : INPUT;
c_d3 : INPUT;
c_d4 : INPUT;
c_d5 : INPUT;
c_d6 : INPUT;
clk : INPUT;
clr : INPUT;
c_u1 : INPUT;
c_u2 : INPUT;
c_u3 : INPUT;
c_u4 : INPUT;
c_u5 : INPUT;
deng : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
d5 : INPUT;
d6 : INPUT;
full : INPUT;
g1 : INPUT;
g2 : INPUT;
g3 : INPUT;
g4 : INPUT;
g5 : INPUT;
g6 : INPUT;
quick : INPUT;
-- Node name is 'alarm'
-- Equation name is 'alarm', type is output
alarm = _LC1_B17;
-- Node name is ':143' = 'cc_d0'
-- Equation name is 'cc_d0', location is LC6_B17, type is buried.
cc_d0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = cc_d0 & clr
# cc_d0 & full
# cc_d0 & q;
-- Node name is ':142' = 'cc_d1'
-- Equation name is 'cc_d1', location is LC7_A13, type is buried.
cc_d1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = c_d22 & _LC4_B17 & !q
# cc_d1 & q
# cc_d1 & !_LC4_B17;
-- Node name is ':141' = 'cc_d2'
-- Equation name is 'cc_d2', location is LC6_A17, type is buried.
cc_d2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = c_d33 & _LC4_B17 & !q
# cc_d2 & q
# cc_d2 & !_LC4_B17;
-- Node name is ':140' = 'cc_d3'
-- Equation name is 'cc_d3', location is LC6_A15, type is buried.
cc_d3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = c_d44 & _LC4_B17 & !q
# cc_d3 & q
# cc_d3 & !_LC4_B17;
-- Node name is ':139' = 'cc_d4'
-- Equation name is 'cc_d4', location is LC6_A5, type is buried.
cc_d4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = c_d55 & _LC4_B17 & !q
# cc_d4 & q
# cc_d4 & !_LC4_B17;
-- Node name is ':138' = 'cc_d5'
-- Equation name is 'cc_d5', location is LC3_A3, type is buried.
cc_d5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = c_d66 & _LC4_B17 & !q
# cc_d5 & q
# cc_d5 & !_LC4_B17;
-- Node name is ':137' = 'cc_u0'
-- Equation name is 'cc_u0', location is LC7_A20, type is buried.
cc_u0 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = c_u11 & _LC4_B17 & !q
# cc_u0 & q
# cc_u0 & !_LC4_B17;
-- Node name is ':136' = 'cc_u1'
-- Equation name is 'cc_u1', location is LC8_A13, type is buried.
cc_u1 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = c_u22 & _LC4_B17 & !q
# cc_u1 & q
# cc_u1 & !_LC4_B17;
-- Node name is ':135' = 'cc_u2'
-- Equation name is 'cc_u2', location is LC7_A17, type is buried.
cc_u2 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = c_u33 & _LC4_B17 & !q
# cc_u2 & q
# cc_u2 & !_LC4_B17;
-- Node name is ':134' = 'cc_u3'
-- Equation name is 'cc_u3', location is LC7_A15, type is buried.
cc_u3 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = c_u44 & _LC4_B17 & !q
# cc_u3 & q
# cc_u3 & !_LC4_B17;
-- Node name is ':133' = 'cc_u4'
-- Equation name is 'cc_u4', location is LC8_A5, type is buried.
cc_u4 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = c_u55 & _LC4_B17 & !q
# cc_u4 & q
# cc_u4 & !_LC4_B17;
-- Node name is ':132' = 'cc_u5'
-- Equation name is 'cc_u5', location is LC3_A2, type is buried.
cc_u5 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = cc_u5 & clr
# cc_u5 & full
# cc_u5 & q;
-- Node name is 'c_d2~1'
-- Equation name is 'c_d2~1', location is LC7_A19, type is buried.
-- synthesized logic cell
_LC7_A19 = LCELL( _EQ013);
_EQ013 = !c_d2 & c_d3 & !_LC8_A3;
-- Node name is 'c_d2~2'
-- Equation name is 'c_d2~2', location is LC2_A19, type is buried.
-- synthesized logic cell
_LC2_A19 = LCELL( _EQ014);
_EQ014 = !c_d2 & !c_d3 & !_LC8_A3;
-- Node name is 'c_d2~3'
-- Equation name is 'c_d2~3', location is LC6_A8, type is buried.
-- synthesized logic cell
_LC6_A8 = LCELL( _EQ015);
_EQ015 = !c_d4 & _LC2_A19;
-- Node name is 'c_d2~4'
-- Equation name is 'c_d2~4', location is LC4_A8, type is buried.
-- synthesized logic cell
_LC4_A8 = LCELL( _EQ016);
_EQ016 = !c_d4 & !c_d5 & c_d6 & _LC2_A19;
-- Node name is ':114' = 'c_d22'
-- Equation name is 'c_d22', location is LC6_A19, type is buried.
c_d22 = DFFE( _EQ017, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = c_d22 & _LC5_A19
# c_d2 & !_LC8_A3;
-- Node name is ':117' = 'c_d33'
-- Equation name is 'c_d33', location is LC3_A19, type is buried.
c_d33 = DFFE( _EQ018, GLOBAL( clk), VCC, VCC, VCC);
_EQ018 = c_d33 & updown
# c_d33 & _LC1_A19
# _LC7_A19;
-- Node name is ':120' = 'c_d44'
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