📄 dianti.rpt
字号:
69 - - A -- INPUT 0 0 0 4 c_u1
18 - - A -- INPUT 0 0 0 3 c_u2
10 - - - 01 INPUT 0 0 0 2 c_u3
3 - - - 12 INPUT 0 0 0 2 c_u4
37 - - - 09 INPUT 0 0 0 1 c_u5
23 - - B -- INPUT 0 0 0 7 deng
79 - - - 24 INPUT 0 0 0 4 d1
47 - - - 14 INPUT 0 0 0 3 d2
80 - - - 23 INPUT 0 0 0 2 d3
73 - - A -- INPUT 0 0 0 3 d4
39 - - - 11 INPUT 0 0 0 2 d5
36 - - - 07 INPUT 0 0 0 1 d6
6 - - - 04 INPUT 0 0 0 11 full
52 - - - 19 INPUT 0 0 0 11 g1
84 - - - -- INPUT 0 0 0 17 g2
42 - - - -- INPUT 0 0 0 16 g3
2 - - - -- INPUT 0 0 0 14 g4
44 - - - -- INPUT 0 0 0 13 g5
54 - - - 21 INPUT 0 0 0 6 g6
24 - - B -- INPUT 0 0 0 8 quick
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\a\dianti.rpt
dianti
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
21 - - B -- OUTPUT 0 1 0 0 alarm
65 - - B -- OUTPUT 0 1 0 0 door0
67 - - B -- OUTPUT 0 1 0 0 door1
66 - - B -- OUTPUT 0 1 0 0 down
59 - - C -- OUTPUT 0 1 0 0 led_c_d0
71 - - A -- OUTPUT 0 1 0 0 led_c_d1
72 - - A -- OUTPUT 0 1 0 0 led_c_d2
49 - - - 16 OUTPUT 0 1 0 0 led_c_d3
19 - - A -- OUTPUT 0 1 0 0 led_c_d4
16 - - A -- OUTPUT 0 1 0 0 led_c_d5
30 - - C -- OUTPUT 0 1 0 0 led_c_u0
83 - - - 13 OUTPUT 0 1 0 0 led_c_u1
50 - - - 17 OUTPUT 0 1 0 0 led_c_u2
17 - - A -- OUTPUT 0 1 0 0 led_c_u3
5 - - - 05 OUTPUT 0 1 0 0 led_c_u4
11 - - - 01 OUTPUT 0 1 0 0 led_c_u5
70 - - A -- OUTPUT 0 1 0 0 led_d0
22 - - B -- OUTPUT 0 1 0 0 led_d1
51 - - - 18 OUTPUT 0 1 0 0 led_d2
48 - - - 15 OUTPUT 0 1 0 0 led_d3
35 - - - 06 OUTPUT 0 1 0 0 led_d4
8 - - - 03 OUTPUT 0 1 0 0 led_d5
58 - - C -- OUTPUT 0 1 0 0 led0
27 - - C -- OUTPUT 0 1 0 0 led1
81 - - - 22 OUTPUT 0 1 0 0 led2
60 - - C -- OUTPUT 0 1 0 0 led3
28 - - C -- OUTPUT 0 1 0 0 led4
61 - - C -- OUTPUT 0 1 0 0 led5
62 - - C -- OUTPUT 0 1 0 0 led6
29 - - C -- OUTPUT 0 1 0 0 ud
25 - - B -- OUTPUT 0 1 0 0 up
64 - - B -- OUTPUT 0 1 0 0 wahaha
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\a\dianti.rpt
dianti
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - A 19 AND2 s 2 1 0 1 c_d2~1
- 2 - A 19 AND2 s 2 1 0 3 c_d2~2
- 6 - A 08 AND2 s 1 1 0 1 c_d2~3
- 4 - A 08 AND2 s 3 1 0 1 c_d2~4
- 2 - C 20 OR2 s ! 0 2 0 12 clr~1
- 1 - B 22 AND2 s 1 1 0 3 clr~2
- 2 - B 13 AND2 s 1 2 0 1 clr~3
- 6 - B 13 AND2 s 0 3 0 1 clr~4
- 7 - B 13 AND2 s 1 3 0 1 clr~5
- 4 - C 18 AND2 s 2 1 0 1 clr~6
- 5 - C 20 AND2 s 4 0 0 2 clr~7
- 7 - C 18 AND2 s 2 2 0 1 clr~8
- 8 - C 18 AND2 s 2 2 0 1 clr~9
- 6 - C 20 AND2 s 3 0 0 1 clr~10
- 8 - C 20 OR2 s 2 1 0 1 clr~11
- 3 - A 04 AND2 s 3 1 0 1 c_u1~1
- 6 - A 04 AND2 s 3 1 0 2 c_u1~2
- 2 - A 24 AND2 s 2 1 0 1 d1~1
- 5 - A 24 AND2 s 2 1 0 1 d1~2
- 6 - A 24 AND2 s 3 1 0 3 d1~3
- 7 - A 12 AND2 s 3 1 0 1 d1~4
- 1 - B 16 DFFE + 1 2 1 0 :28
- 8 - B 22 DFFE + 2 1 1 2 :30
- 1 - C 20 DFFE + 0 3 1 0 :32
- 3 - C 20 DFFE + 0 3 1 0 :34
- 2 - C 18 DFFE + 0 3 1 0 :36
- 4 - C 20 DFFE + 0 3 1 0 :38
- 6 - A 22 DFFE + 1 3 1 1 :40
- 1 - C 18 DFFE + 0 3 1 0 :42
- 6 - C 18 DFFE + 1 2 1 0 :44
- 1 - A 02 DFFE + 0 1 1 0 :46
- 5 - A 05 DFFE + 0 1 1 0 :48
- 3 - A 15 DFFE + 0 1 1 0 :50
- 4 - A 17 DFFE + 0 1 1 0 :52
- 3 - A 13 DFFE + 0 1 1 0 :54
- 7 - A 16 DFFE + 0 1 1 0 :56
- 1 - A 03 DFFE + 0 1 1 0 :58
- 7 - A 05 DFFE + 0 1 1 0 :60
- 2 - A 15 DFFE + 0 1 1 0 :62
- 3 - A 17 DFFE + 0 1 1 0 :64
- 4 - A 13 DFFE + 0 1 1 0 :66
- 5 - C 15 DFFE + 0 1 1 0 :68
- 4 - A 03 DFFE + 0 1 1 0 :70
- 4 - A 05 DFFE + 0 1 1 0 :72
- 8 - A 15 DFFE + 0 1 1 0 :74
- 8 - A 17 DFFE + 0 1 1 0 :76
- 2 - A 13 DFFE + 0 1 1 0 :78
- 8 - A 20 DFFE + 0 1 1 0 :80
- 6 - B 18 DFFE + 1 2 1 0 :82
- 5 - C 19 DFFE + 0 1 1 0 :84
- 1 - B 17 DFFE + 2 0 1 0 :86
- 8 - B 13 DFFE + 0 3 1 0 :88
- 3 - B 13 DFFE + 0 3 1 0 :90
- 7 - B 19 DFFE + 0 3 0 5 q12 (:92)
- 3 - B 20 DFFE + 0 3 0 4 q11 (:93)
- 1 - B 20 DFFE + 0 3 0 5 q10 (:94)
- 8 - B 21 DFFE + 1 2 0 2 q23 (:95)
- 4 - B 21 DFFE + 1 2 0 3 q22 (:96)
- 8 - B 18 DFFE + 1 3 0 6 q21 (:97)
- 5 - B 17 DFFE + 1 2 0 6 q20 (:98)
- 2 - B 17 DFFE + 2 0 0 31 q (:99)
- 7 - B 15 DFFE + 2 1 0 15 opendoor (:100)
- 4 - A 18 DFFE + 0 3 0 6 en_up (:101)
- 1 - B 13 DFFE + 0 4 0 26 updown (:102)
- 1 - A 18 DFFE + 0 3 0 3 en_dw (:103)
- 2 - A 20 DFFE + 1 2 0 2 d11 (:104)
- 4 - A 20 DFFE + 1 2 0 2 c_u11 (:105)
- 2 - A 02 DFFE + 0 3 0 6 dd_cc5 (:106)
- 2 - A 05 DFFE + 0 3 0 4 dd_cc4 (:107)
- 5 - A 15 DFFE + 0 3 0 3 dd_cc3 (:108)
- 2 - A 17 DFFE + 0 3 0 4 dd_cc2 (:109)
- 1 - A 13 DFFE + 0 3 0 3 dd_cc1 (:110)
- 1 - A 21 DFFE + 0 3 0 1 dd_cc0 (:111)
- 1 - A 24 DFFE + 1 2 0 5 d22 (:112)
- 2 - A 22 DFFE + 2 2 0 4 c_u22 (:113)
- 6 - A 19 DFFE + 1 2 0 3 c_d22 (:114)
- 8 - A 24 DFFE + 1 2 0 5 d33 (:115)
- 2 - A 04 DFFE + 0 3 0 3 c_u33 (:116)
- 3 - A 19 DFFE + 0 3 0 3 c_d33 (:117)
- 4 - A 24 DFFE + 1 2 0 5 d44 (:118)
- 1 - A 04 DFFE + 1 2 0 3 c_u44 (:119)
- 8 - A 08 DFFE + 1 2 0 3 c_d44 (:120)
- 4 - A 12 DFFE + 2 2 0 6 d55 (:121)
- 8 - A 04 DFFE + 2 2 0 4 c_u55 (:122)
- 1 - A 08 DFFE + 1 2 0 3 c_d55 (:123)
- 6 - A 12 DFFE + 0 3 0 2 d66 (:124)
- 5 - A 12 DFFE + 0 3 0 2 c_d66 (:125)
- 2 - A 03 DFFE + 0 3 0 2 dd5 (:126)
- 3 - A 05 DFFE + 0 3 0 2 dd4 (:127)
- 4 - A 15 DFFE + 0 3 0 2 dd3 (:128)
- 5 - A 17 DFFE + 0 3 0 2 dd2 (:129)
- 6 - A 13 DFFE + 0 3 0 2 dd1 (:130)
- 5 - A 20 DFFE + 0 3 0 2 dd0 (:131)
- 3 - A 02 DFFE + 2 1 0 2 cc_u5 (:132)
- 8 - A 05 DFFE + 0 3 0 2 cc_u4 (:133)
- 7 - A 15 DFFE + 0 3 0 2 cc_u3 (:134)
- 7 - A 17 DFFE + 0 3 0 2 cc_u2 (:135)
- 8 - A 13 DFFE + 0 3 0 2 cc_u1 (:136)
- 7 - A 20 DFFE + 0 3 0 2 cc_u0 (:137)
- 3 - A 03 DFFE + 0 3 0 2 cc_d5 (:138)
- 6 - A 05 DFFE + 0 3 0 2 cc_d4 (:139)
- 6 - A 15 DFFE + 0 3 0 2 cc_d3 (:140)
- 6 - A 17 DFFE + 0 3 0 2 cc_d2 (:141)
- 7 - A 13 DFFE + 0 3 0 2 cc_d1 (:142)
- 6 - B 17 DFFE + 2 1 0 2 cc_d0 (:143)
- 1 - A 06 AND2 s 0 3 0 2 ~466~1
- 2 - A 06 AND2 s 2 1 0 1 ~466~2
- 4 - A 06 AND2 s 0 3 0 2 ~466~3
- 7 - A 06 AND2 s 1 2 0 1 ~466~4
- 3 - A 08 AND2 s 0 3 0 2 ~466~5
- 4 - A 09 AND2 s 0 3 0 2 ~466~6
- 1 - A 09 AND2 s 1 2 0 1 ~466~7
- 5 - A 06 AND2 s 0 3 0 2 ~466~8
- 4 - A 19 AND2 s 0 3 0 2 ~466~9
- 5 - A 23 AND2 s 0 3 0 2 ~466~10
- 8 - A 19 AND2 s 0 3 0 2 ~466~11
- 1 - B 21 AND2 0 4 0 18 :466
- 2 - B 19 AND2 0 3 0 5 :533
- 1 - B 19 OR2 ! 0 3 0 2 :542
- 4 - B 20 OR2 s ! 1 1 0 1 ~1020~1
- 4 - B 19 OR2 1 3 0 1 :1239
- 3 - B 19 OR2 s 1 3 0 2 ~1240~1
- 5 - B 19 OR2 1 3 0 1 :1242
- 6 - A 20 AND2 ! 0 2 0 2 :1378
- 8 - A 21 AND2 0 4 0 1 :1496
- 2 - A 18 AND2 0 2 0 3 :1548
- 4 - A 21 AND2 ! 0 2 0 5 :1634
- 3 - A 21 AND2 0 4 0 2 :1779
- 6 - A 21 OR2 0 4 0 1 :1902
- 5 - A 21 OR2 0 4 0 1 :1903
- 8 - A 11 AND2 ! 0 2 0 6 :2043
- 6 - A 07 AND2 0 4 0 2 :2188
- 8 - A 07 OR2 0 4 0 1 :2311
- 7 - A 07 OR2 0 4 0 1 :2312
- 6 - A 10 AND2 ! 0 2 0 5 :2452
- 1 - A 07 AND2 0 4 0 2 :2597
- 4 - A 07 OR2 0 4 0 1 :2720
- 3 - A 07 OR2 0 4 0 1 :2721
- 5 - A 09 AND2 0 3 0 2 :3006
- 7 - A 09 OR2 0 4 0 1 :3129
- 6 - A 09 OR2 0 4 0 1 :3130
- 8 - A 12 AND2 ! 0 2 0 2 :3165
- 3 - A 12 AND2 s ! 2 0 0 4 ~3317~1
- 3 - C 18 AND2 s 3 0 0 3 ~3664~1
- 3 - A 09 OR2 1 3 0 1 :3818
- 8 - A 09 OR2 1 3 0 1 :3821
- 5 - A 07 OR2 1 3 0 1 :3824
- 2 - A 07 OR2 1 3 0 1 :3827
- 7 - A 21 OR2 1 3 0 1 :3830
- 2 - A 21 OR2 1 3 0 1 :3833
- 4 - B 15 AND2 s 0 2 0 6 ~3897~1
- 6 - B 19 OR2 0 4 0 1 :3901
- 6 - A 03 OR2 s 0 2 0 1 ~4856~1
- 1 - A 05 OR2 s 0 2 0 1 ~4857~1
- 1 - A 15 OR2 s 0 2 0 1 ~4858~1
- 1 - A 17 OR2 s 0 2 0 1 ~4859~1
- 5 - A 13 OR2 s 0 2 0 1 ~4860~1
- 3 - A 20 OR2 s 0 2 0 1 ~4861~1
- 8 - A 03 OR2 s 0 2 0 17 ~5207~1
- 2 - B 22 OR2 s 1 2 0 1 ~5231~1
- 4 - B 13 OR2 s 0 4 0 1 ~5231~2
- 5 - B 13 OR2 s 0 3 0 2 ~5255~1
- 5 - A 08 OR2 s 1 2 0 1 ~5291~1
- 1 - A 12 OR2 s 2 2 0 1 ~5303~1
- 7 - A 04 OR2 s 1 3 0 1 ~5315~1
- 2 - A 08 OR2 s 1 2 0 1 ~5327~1
- 7 - A 24 OR2 s 2 1 0 1 ~5339~1
- 4 - A 04 OR2 s 1 2 0 1 ~5351~1
- 1 - A 19 OR2 s 2 1 0 2 ~5363~1
- 3 - A 24 OR2 s 2 1 0 1 ~5375~1
- 5 - A 19 OR2 s 1 2 0 1 ~5399~1
- 6 - A 06 OR2 s 0 3 0 1 ~5411~1
- 2 - A 09 OR2 s 0 4 0 1 ~5411~2
- 3 - A 11 OR2 s 1 3 0 1 ~5411~3
- 4 - A 11 OR2 s 1 3 0 1 ~5411~4
- 1 - A 11 OR2 s 1 3 0 1 ~5411~5
- 3 - A 18 OR2 s 0 3 0 1 ~5411~6
- 5 - A 18 OR2 s 1 3 0 1 ~5411~7
- 1 - A 22 OR2 s ! 1 1 0 7 ~5411~8
- 8 - A 22 OR2 s 2 1 0 4 ~5411~9
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -