📄 dianti1.rpt
字号:
- 2 - A 01 OR2 0 4 0 1 |DIANTI:1|:2721
- 7 - A 02 AND2 0 3 0 2 |DIANTI:1|:3006
- 2 - A 12 OR2 0 4 0 1 |DIANTI:1|:3129
- 1 - A 05 OR2 0 4 0 1 |DIANTI:1|:3130
- 6 - A 02 OR2 0 2 0 1 |DIANTI:1|:3165
- 8 - A 20 AND2 s 3 0 0 3 |DIANTI:1|~3664~1
- 8 - A 02 OR2 1 3 0 1 |DIANTI:1|:3818
- 5 - A 02 OR2 1 3 0 1 |DIANTI:1|:3821
- 4 - A 01 OR2 1 3 0 1 |DIANTI:1|:3824
- 7 - A 01 OR2 1 3 0 1 |DIANTI:1|:3827
- 5 - A 17 OR2 1 3 0 1 |DIANTI:1|:3830
- 7 - A 17 OR2 1 3 0 1 |DIANTI:1|:3833
- 2 - C 15 AND2 s 0 2 0 6 |DIANTI:1|~3897~1
- 7 - C 15 OR2 0 4 0 1 |DIANTI:1|:3901
- 3 - A 03 OR2 s 0 2 0 1 |DIANTI:1|~4856~1
- 2 - A 10 OR2 s 0 2 0 1 |DIANTI:1|~4857~1
- 1 - A 06 OR2 s 0 2 0 1 |DIANTI:1|~4858~1
- 1 - A 11 OR2 s 0 2 0 1 |DIANTI:1|~4859~1
- 1 - A 16 OR2 s 0 2 0 1 |DIANTI:1|~4860~1
- 4 - B 14 OR2 s 0 2 0 1 |DIANTI:1|~4861~1
- 5 - C 22 OR2 s 0 2 0 18 |DIANTI:1|~5207~1
- 8 - C 18 OR2 s 0 2 0 13 |DIANTI:1|~5231~1
- 4 - C 13 OR2 s 1 2 0 1 |DIANTI:1|~5231~2
- 5 - C 13 OR2 s 0 4 0 1 |DIANTI:1|~5231~3
- 1 - C 18 OR2 s 0 3 0 2 |DIANTI:1|~5243~1
- 7 - C 18 OR2 s 0 2 0 7 |DIANTI:1|~5279~1
- 3 - A 20 OR2 s 3 1 0 2 |DIANTI:1|~5279~2
- 2 - A 05 OR2 s 2 2 0 1 |DIANTI:1|~5291~1
- 5 - A 13 OR2 s 2 2 0 1 |DIANTI:1|~5303~1
- 7 - A 12 OR2 s 1 3 0 1 |DIANTI:1|~5315~1
- 4 - A 04 OR2 s 1 2 0 1 |DIANTI:1|~5327~1
- 3 - A 13 OR2 s 2 1 0 1 |DIANTI:1|~5339~1
- 4 - A 12 OR2 s 1 2 0 1 |DIANTI:1|~5351~1
- 1 - B 19 OR2 s 3 1 0 1 |DIANTI:1|~5375~1
- 5 - A 14 OR2 s 2 1 0 2 |DIANTI:1|~5387~1
- 3 - A 18 OR2 s 1 2 0 1 |DIANTI:1|~5399~1
- 1 - A 04 OR2 s 0 3 0 1 |DIANTI:1|~5411~1
- 1 - A 02 OR2 s 0 4 0 1 |DIANTI:1|~5411~2
- 1 - A 07 OR2 s 1 3 0 1 |DIANTI:1|~5411~3
- 2 - A 07 OR2 s 1 3 0 1 |DIANTI:1|~5411~4
- 4 - A 15 OR2 s 0 3 0 1 |DIANTI:1|~5411~5
- 5 - A 15 OR2 s 1 3 0 1 |DIANTI:1|~5411~6
- 4 - A 23 OR2 s ! 1 1 0 6 |DIANTI:1|~5411~7
- 6 - A 20 OR2 s 2 1 0 8 |DIANTI:1|~5411~8
- 5 - A 20 OR2 s 3 1 0 2 |DIANTI:1|~5411~9
- 6 - A 12 OR2 s 1 1 0 1 |DIANTI:1|~5411~10
- 3 - A 14 OR2 s 1 3 0 1 |DIANTI:1|~5435~1
- 6 - B 22 OR2 s 1 3 0 1 |DIANTI:1|~5459~1
- 4 - A 20 OR2 s 4 0 0 2 |DIANTI:1|~5483~1
- 2 - B 22 OR2 s 2 2 0 1 |DIANTI:1|~5495~1
- 3 - B 22 OR2 s 4 0 0 1 |DIANTI:1|~5495~2
- 5 - B 19 OR2 s 3 0 0 1 |DIANTI:1|~5507~1
- 3 - A 07 OR2 s 0 4 0 1 |DIANTI:1|~5531~1
- 5 - A 07 AND2 s 2 2 0 1 |DIANTI:1|~5531~2
- 6 - A 07 OR2 s 1 2 0 1 |DIANTI:1|~5531~3
- 7 - A 07 OR2 s 0 4 0 1 |DIANTI:1|~5531~4
- 8 - A 07 OR2 s 0 4 0 1 |DIANTI:1|~5531~5
- 4 - A 07 OR2 s 1 3 0 1 |DIANTI:1|~5531~6
- 6 - A 15 OR2 s 0 3 0 1 |DIANTI:1|~5531~7
- 7 - A 15 OR2 s 1 3 0 1 |DIANTI:1|~5531~8
- 8 - A 15 OR2 s 1 3 0 1 |DIANTI:1|~5531~9
- 5 - B 22 OR2 s 1 2 0 2 |DIANTI:1|~5555~1
- 8 - A 17 OR2 0 4 0 1 |DIANTI:1|:5561
- 5 - C 16 OR2 s 0 2 0 1 |DIANTI:1|~5591~1
- 7 - C 16 OR2 s 2 2 0 1 |DIANTI:1|~5591~2
- 8 - C 16 OR2 s 1 3 0 1 |DIANTI:1|~5591~3
- 1 - C 13 OR2 s 1 3 0 3 |DIANTI:1|~5603~1
- 3 - C 16 OR2 s 1 2 0 1 |DIANTI:1|~5603~2
- 4 - C 16 OR2 s 0 4 0 1 |DIANTI:1|~5603~3
- 4 - B 16 OR2 s ! 2 0 0 21 |DIANTI:1|~5617~1
- 6 - C 13 AND2 s 1 2 0 3 |DIANTI:1|~5617~2
- 2 - C 16 AND2 s 1 3 0 1 |DIANTI:1|~5617~3
- 3 - C 14 OR2 s 0 4 0 1 |DIANTI:1|~5629~1
- 6 - C 14 AND2 s 0 2 0 1 |DIANTI:1|~5629~2
- 2 - C 14 OR2 s 0 4 0 3 |DIANTI:1|~5641~1
- 7 - C 14 OR2 s 1 2 0 1 |DIANTI:1|~5641~2
- 8 - C 14 AND2 s 0 3 0 1 |DIANTI:1|~5641~3
- 1 - B 18 AND2 s 1 2 0 2 |DIANTI:1|~5653~1
- 5 - B 23 AND2 s ! 0 4 0 2 |DIANTI:1|~5653~2
- 6 - B 23 OR2 s 0 4 0 1 |DIANTI:1|~5653~3
- 7 - B 23 AND2 s 0 3 0 1 |DIANTI:1|~5653~4
- 5 - B 16 OR2 s 1 1 0 7 |DIANTI:1|~5665~1
- 7 - B 13 OR2 s 0 3 0 1 |DIANTI:1|~5665~2
- 6 - B 13 OR2 s 0 4 0 1 |DIANTI:1|~5665~3
- 1 - B 23 AND2 s 0 3 0 1 |DIANTI:1|~5665~4
- 2 - B 23 AND2 s 0 3 0 1 |DIANTI:1|~5665~5
- 1 - B 13 OR2 s 0 2 0 2 |DIANTI:1|~5677~1
- 2 - B 13 OR2 s 0 4 0 1 |DIANTI:1|~5677~2
- 3 - B 13 OR2 s 0 4 0 1 |DIANTI:1|~5677~3
- 2 - C 13 AND2 s ! 0 2 0 3 |DIANTI:1|~5689~1
- 8 - C 13 OR2 s 1 1 0 6 |DIANTI:1|~5689~2
- 4 - B 13 OR2 s 0 3 0 2 |DIANTI:1|~5689~3
- 3 - B 16 AND2 s 0 3 0 1 |DIANTI:1|~5689~4
- 7 - B 16 OR2 s 0 3 0 1 |DIANTI:1|~5689~5
- 4 - A 18 AND2 s 2 1 0 1 D1~1
- 8 - A 18 AND2 s 2 1 0 1 D1~2
- 4 - A 13 AND2 s 3 1 0 3 D1~3
- 7 - A 13 AND2 s 3 1 0 1 D1~4
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\a\dianti1.rpt
dianti1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 36/ 96( 37%) 28/ 48( 58%) 25/ 48( 52%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
B: 7/ 96( 7%) 2/ 48( 4%) 24/ 48( 50%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 7/ 96( 7%) 2/ 48( 4%) 21/ 48( 43%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 5/24( 20%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 4/24( 16%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\a\dianti1.rpt
dianti1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 84 CLK
Device-Specific Information: e:\a\dianti1.rpt
dianti1
** EQUATIONS **
C_D2 : INPUT;
C_D3 : INPUT;
C_D4 : INPUT;
C_D5 : INPUT;
C_D6 : INPUT;
CLK : INPUT;
CLR : INPUT;
C_U1 : INPUT;
C_U2 : INPUT;
C_U3 : INPUT;
C_U4 : INPUT;
C_U5 : INPUT;
DENG : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
D4 : INPUT;
D5 : INPUT;
D6 : INPUT;
FULL : INPUT;
G1 : INPUT;
G2 : INPUT;
G3 : INPUT;
G4 : INPUT;
G5 : INPUT;
G6 : INPUT;
QUICK : INPUT;
-- Node name is 'alarm'
-- Equation name is 'alarm', type is output
alarm = _LC2_B16;
-- Node name is 'C_D2~1'
-- Equation name is 'C_D2~1', location is LC8_A14, type is buried.
-- synthesized logic cell
_LC8_A14 = LCELL( _EQ001);
_EQ001 = !C_D2 & C_D3 & !_LC5_C22;
-- Node name is 'C_D2~2'
-- Equation name is 'C_D2~2', location is LC8_A5, type is buried.
-- synthesized logic cell
_LC8_A5 = LCELL( _EQ002);
_EQ002 = !C_D2 & !C_D3 & !_LC5_C22;
-- Node name is 'C_D2~3'
-- Equation name is 'C_D2~3', location is LC5_A5, type is buried.
-- synthesized logic cell
_LC5_A5 = LCELL( _EQ003);
_EQ003 = !C_D2 & !C_D3 & !C_D4 & !_LC5_C22;
-- Node name is 'C_D2~4'
-- Equation name is 'C_D2~4', location is LC7_A5, type is buried.
-- synthesized logic cell
_LC7_A5 = LCELL( _EQ004);
_EQ004 = !C_D5 & C_D6;
-- Node name is 'CLR~1'
-- Equation name is 'CLR~1', location is LC3_C13, type is buried.
-- synthesized logic cell
_LC3_C13 = LCELL( _EQ005);
_EQ005 = !DENG & _LC1_A15 & _LC4_C15 & !QUICK;
-- Node name is 'CLR~2'
-- Equation name is 'CLR~2', location is LC4_C18, type is buried.
-- synthesized logic cell
_LC4_C18 = LCELL( _EQ006);
_EQ006 = _LC4_C15 & !QUICK;
-- Node name is 'CLR~3'
-- Equation name is 'CLR~3', location is LC5_C18, type is buried.
-- synthesized logic cell
_LC5_C18 = LCELL( _EQ007);
_EQ007 = !DENG & _LC1_A15 & _LC4_C18 & !_LC7_C18;
-- Node name is 'CLR~4'
-- Equation name is 'CLR~4', location is LC6_C18, type is buried.
-- synthesized logic cell
_LC6_C18 = LCELL( _EQ008);
_EQ008 = _LC4_C15 & _LC6_C13 & !_LC7_C18 & !QUICK;
-- Node name is 'CLR~5'
-- Equation name is 'CLR~5', location is LC3_B19, type is buried.
-- synthesized logic cell
_LC3_B19 = LCELL( _EQ009);
_EQ009 = !G2 & !G3 & _LC8_A20;
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