uart_regs.map.qmsg

many examples of fpga

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 uart_regs.v(476) " "Warning: Verilog HDL expression warning at uart_regs.v(476): truncated operand with size 2 to match size of smaller operand (1)" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 476 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 uart_regs.v(487) " "Warning: Verilog HDL expression warning at uart_regs.v(487): truncated operand with size 32 to match size of smaller operand (1)" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 487 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartus/libraries/megafunctions/scfifo.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file e:/quartus/libraries/megafunctions/scfifo.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo " "Info: Found entity 1: scfifo" {  } { { "e:/quartus/libraries/megafunctions/scfifo.tdf" "scfifo" "" { Text "e:/quartus/libraries/megafunctions/scfifo.tdf" 239 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_eaq.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/scfifo_eaq.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_eaq " "Info: Found entity 1: scfifo_eaq" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/scfifo_eaq.tdf" "scfifo_eaq" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/scfifo_eaq.tdf" 30 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_rll.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/a_dpfifo_rll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_rll " "Info: Found entity 1: a_dpfifo_rll" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/a_dpfifo_rll.tdf" "a_dpfifo_rll" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/a_dpfifo_rll.tdf" 35 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_qve.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/a_fefifo_qve.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_qve " "Info: Found entity 1: a_fefifo_qve" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/a_fefifo_qve.tdf" "a_fefifo_qve" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/a_fefifo_qve.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file e:/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "e:/quartus/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "e:/quartus/libraries/megafunctions/lpm_counter.tdf" 221 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_stratix " "Info: Found entity 1: alt_counter_stratix" {  } { { "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "alt_counter_stratix" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 282 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_81k.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/dpram_81k.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_81k " "Info: Found entity 1: dpram_81k" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/dpram_81k.tdf" "dpram_81k" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/dpram_81k.tdf" 30 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_mmb1.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/altsyncram_mmb1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_mmb1 " "Info: Found entity 1: altsyncram_mmb1" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/altsyncram_mmb1.tdf" "altsyncram_mmb1" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/altsyncram_mmb1.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 uart_receiver.v(206) " "Warning: Verilog HDL expression warning at uart_receiver.v(206): truncated operand with size 32 to match size of smaller operand (8)" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_receiver.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_receiver.v" 206 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 uart_receiver.v(221) " "Warning: Verilog HDL expression warning at uart_receiver.v(221): truncated operand with size 32 to match size of smaller operand (10)" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_receiver.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_receiver.v" 221 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_nbq.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/scfifo_nbq.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_nbq " "Info: Found entity 1: scfifo_nbq" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/scfifo_nbq.tdf" "scfifo_nbq" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/scfifo_nbq.tdf" 30 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_4nl.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/a_dpfifo_4nl.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_4nl " "Info: Found entity 1: a_dpfifo_4nl" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/a_dpfifo_4nl.tdf" "a_dpfifo_4nl" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/a_dpfifo_4nl.tdf" 35 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_h2k.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/dpram_h2k.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_h2k " "Info: Found entity 1: dpram_h2k" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/dpram_h2k.tdf" "dpram_h2k" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/dpram_h2k.tdf" 30 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_apb1.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/altsyncram_apb1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_apb1 " "Info: Found entity 1: altsyncram_apb1" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/altsyncram_apb1.tdf" "altsyncram_apb1" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/dev/db/altsyncram_apb1.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartus/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file e:/quartus/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "e:/quartus/libraries/megafunctions/lpm_add_sub.tdf" "lpm_add_sub" "" { Text "e:/quartus/libraries/megafunctions/lpm_add_sub.tdf" 103 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartus/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file e:/quartus/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "e:/quartus/libraries/megafunctions/addcore.tdf" "addcore" "" { Text "e:/quartus/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartus/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file e:/quartus/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "e:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "a_csnbuffer" "" { Text "e:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartus/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file e:/quartus/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "e:/quartus/libraries/megafunctions/altshift.tdf" "altshift" "" { Text "e:/quartus/libraries/megafunctions/altshift.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 31 13:39:55 2004 " "Info: Processing ended: Fri Dec 31 13:39:55 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}