uart_regs.sim.qmsg

many examples of fpga

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jan 14 21:32:26 2005 " "Info: Processing started: Fri Jan 14 21:32:26 2005" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --import_settings_files=on --export_settings_files=off uart_regs -c uart_regs " "Info: Command: quartus_sim --import_settings_files=on --export_settings_files=off uart_regs -c uart_regs" {  } {  } 0}
{ "Warning" "WSIM_YGR_AUTO_WRITE_ON_NEG_EDGE" "uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a0 " "Warning: Write to auto-size memory block uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a0 assumed to occur on falling edge of input clock" {  } {  } 0}
{ "Warning" "WSIM_YGR_AUTO_WRITE_ON_NEG_EDGE" "uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a1 " "Warning: Write to auto-size memory block uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a1 assumed to occur on falling edge of input clock" {  } {  } 0}
{ "Warning" "WSIM_YGR_AUTO_WRITE_ON_NEG_EDGE" "uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a2 " "Warning: Write to auto-size memory block uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a2 assumed to occur on falling edge of input clock" {  } {  } 0}
{ "Warning" "WSIM_YGR_AUTO_WRITE_ON_NEG_EDGE" "uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a3 " "Warning: Write to auto-size memory block uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a3 assumed to occur on falling edge of input clock" {  } {  } 0}
{ "Warning" "WSIM_YGR_AUTO_WRITE_ON_NEG_EDGE" "uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a4 " "Warning: Write to auto-size memory block uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a4 assumed to occur on falling edge of input clock" {  } {  } 0}
{ "Warning" "WSIM_YGR_AUTO_WRITE_ON_NEG_EDGE" "uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a5 " "Warning: Write to auto-size memory block uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a5 assumed to occur on falling edge of input clock" {  } {  } 0}
{ "Warning" "WSIM_YGR_AUTO_WRITE_ON_NEG_EDGE" "uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a6 " "Warning: Write to auto-size memory block uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a6 assumed to occur on falling edge of input clock" {  } {  } 0}
{ "Warning" "WSIM_YGR_AUTO_WRITE_ON_NEG_EDGE" "uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a7 " "Warning: Write to auto-size memory block uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a7 assumed to occur on falling edge of input clock" {  } {  } 0}
{ "Warning" "WSIM_YGR_AUTO_WRITE_ON_NEG_EDGE" "uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a8 " "Warning: Write to auto-size memory block uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a8 assumed to occur on falling edge of input clock" {  } {  } 0}
{ "Warning" "WSIM_YGR_AUTO_WRITE_ON_NEG_EDGE" "uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a9 " "Warning: Write to auto-size memory block uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_nbq:auto_generated\|a_dpfifo_4nl:dpfifo\|dpram_h2k:FIFOram\|altsyncram_apb1:altsyncram1\|ram_block2a9 assumed to occur on falling edge of input clock" {  } {  } 0}
{ "Warning" "WSIM_YGR_AUTO_WRITE_ON_NEG_EDGE" "uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a0 " "Warning: Write to auto-size memory block uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a0 assumed to occur on falling edge of input clock" {  } {  } 0}
{ "Warning" "WSIM_YGR_AUTO_WRITE_ON_NEG_EDGE" "uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a1 " "Warning: Write to auto-size memory block uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a1 assumed to occur on falling edge of input clock" {  } {  } 0}
{ "Warning" "WSIM_YGR_AUTO_WRITE_ON_NEG_EDGE" "uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a2 " "Warning: Write to auto-size memory block uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a2 assumed to occur on falling edge of input clock" {  } {  } 0}
{ "Warning" "WSIM_YGR_AUTO_WRITE_ON_NEG_EDGE" "uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a3 " "Warning: Write to auto-size memory block uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a3 assumed to occur on falling edge of input clock" {  } {  } 0}
{ "Warning" "WSIM_YGR_AUTO_WRITE_ON_NEG_EDGE" "uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a4 " "Warning: Write to auto-size memory block uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a4 assumed to occur on falling edge of input clock" {  } {  } 0}
{ "Warning" "WSIM_YGR_AUTO_WRITE_ON_NEG_EDGE" "uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a5 " "Warning: Write to auto-size memory block uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a5 assumed to occur on falling edge of input clock" {  } {  } 0}
{ "Warning" "WSIM_YGR_AUTO_WRITE_ON_NEG_EDGE" "uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a6 " "Warning: Write to auto-size memory block uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a6 assumed to occur on falling edge of input clock" {  } {  } 0}
{ "Warning" "WSIM_YGR_AUTO_WRITE_ON_NEG_EDGE" "uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a7 " "Warning: Write to auto-size memory block uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_eaq:auto_generated\|a_dpfifo_rll:dpfifo\|dpram_81k:FIFOram\|altsyncram_mmb1:altsyncram1\|ram_block2a7 assumed to occur on falling edge of input clock" {  } {  } 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     46.27 % " "Info: Simulation coverage is      46.27 %" {  } {  } 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "371862 " "Info: Number of transitions in simulation is 371862" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 18 s " "Info: Quartus II Simulator was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jan 14 21:32:38 2005 " "Info: Processing ended: Fri Jan 14 21:32:38 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0}  } {  } 0}