s3c24a0_smc.c

nandflash k9g808u0a在pxa270的驱动,由于pxa270没有nandflash接口

/*
 *  drivers/mtd/nand/s3c24a0_smc.c
 *
 * Copyright (C) 2005  Samsung Electronics
 *
 * Derived from drivers/mtd/autcpu12.c
 *       Copyright (c) 2001 Thomas Gleixner ([e-mail])
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 * 
 *  Overview:
 *   This is a device driver for the NAND flash device found on the
 *   Samsung S3C24A0  which is a SmartMediaCard. It supports 
 *   16MiB, 32MiB and 64MiB cards.
 *
 */


#include <linux/slab.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/sizes.h>
                                                                                                                             
/*
 * MTD structure for SMDK24A0 board
 */
static struct mtd_info *s3csmc_mtd = NULL;
                                                                                                                             

/*
 * Define partitions for flash devices
 */
static struct mtd_partition partition_info16M[] = {
        {
                .name	 = "NAND partition 0 : Bootloader",
                .offset  = 0,
                .size    = (192*SZ_1K),
                /* mask_flags:  MTD_WRITEABLE, */
        },
        {
                .name    = "NAND partition 1 : Kernel",
                .offset  = (192*SZ_1K),
                .size    = (2*SZ_1M) - (192*SZ_1K),
        },
        {
                .name	= "NAND partition 2",
                .offset	= (2*SZ_1M),
                .size	= (16*SZ_1M) - (2*SZ_1M),
        },
};
                                                                                                                             
static struct mtd_partition partition_info32M[] = {
        {
                .name	= "NAND partition 0 : Bootloader",
                .offset	= 0,
                .size	= (192*SZ_1K),
        },
        {
                .name	= "NAND partition 1 : Kernel",
                .offset	= (192*SZ_1K),
                .size	= (2*SZ_1M) - (192*SZ_1K),
        },
        {
                .name	= "NAND partition 2",
                .offset	= (2*SZ_1M),
                .size	= (32*SZ_1M) - (2*SZ_1M),
        },
};
static struct mtd_partition partition_info64M[] = {
        {
                .name	= "NAND partition 0 : Bootloader",
                .offset	= 0,
                .size	= (192*SZ_1K),
        },
        {
                .name	= "NAND partition 1 : Kernel",
                .offset	= (192*SZ_1K),    /* Block number is 0xC */
                .size	= (2*SZ_1M) - (192*SZ_1K),
        },
        {
                .name	= "NAND partition 2 : NAND Root ",
                .offset	= (2*SZ_1M),      /* Block number is 0x80*/
                .size	= (50*SZ_1M) - (2*SZ_1M),
        },
        {
                .name	= "NAND partition 3",
                .offset	= (50*SZ_1M),
                .size	= (14*SZ_1M),
        },
};
static struct mtd_partition partition_info128M[] = {
        {
                .name	= "NAND partition 0 : Bootloader",
                .offset	= 0,
                .size	= (192*SZ_1K),
        },
        {
                .name	= "NAND partition 1 : Kernel",
                .offset	= (192*SZ_1K),
                .size	= (2*SZ_1M) - (192*SZ_1K),
        },
        {
                .name	= "NAND partition 2",
                .offset	= (2*SZ_1M),
                .size	= (50*SZ_1M) - (2*SZ_1M),
        },
        {
                .name	= "NAND partition 3",
                .offset	= (50*SZ_1M),
                .size	= (14*SZ_1M),
        },
        {
                .name	= "NAND partition 4",
                .offset	= (64*SZ_1M),
                .size	= (64*SZ_1M),
        },
};
                                                                                                                             

#define NUM_PARTITIONS16M       3
#define NUM_PARTITIONS32M       3
#define NUM_PARTITIONS64M       4
#define NUM_PARTITIONS128M      5



#define SEL_MIN(x,y)                    (((x) < (y)) ? (x) : (y))
                                                                                                                             
extern unsigned long elfin_get_bus_clk(int who);
#define GET_HCLK        1
#define GET_HCLK_NUM(ns)        ((((elfin_get_bus_clk(GET_HCLK)/1000000)*ns)+500)/1000)

/****************************************************************************
 * for S3C24A0
 ****************************************************************************/
#define NFCONF_KeepMask                 \
(                                                               \
        m1NFCONF_AdvanceFlash   |       \
        m1NFCONF_TCEH                   |       \
        m1NFCONF_X16Device              |       \
        m1NFCONF_BusWidth               |       \
        m1NFCONF_PageSize               |       \
        m1NFCONF_AddressCycle           \
)
#define NFCONF_InitSet                                                                  \
(                                                                                                               \
        sNFCONF_TACLS(SEL_MIN(GET_HCLK_NUM(10),0x7))    |       \
        sNFCONF_TWRPH0(SEL_MIN(GET_HCLK_NUM(50)-1,0x7)) |       \
        sNFCONF_TWRPH1(SEL_MIN(GET_HCLK_NUM(30)-1,0x7)) |       \
        sNFCONF_Hardware_nCE(1)                                                         \
)


#define NFCONT_InitSet                          \
(                                                                       \
        sNFCONT_LdStrAddr(0)            |       \
        sNFCONT_EnbIllegalAccINT(0)     |       \
        sNFCONT_EnbLoadINT(0)           |       \
        sNFCONT_EnbStoreINT(0)          |       \
        sNFCONT_EnbRnBINT(0)            |       \
        sNFCONT_RnB_TransMode(0)        |       \
        sNFCONT_SpareECCLock(1)         |       \
        sNFCONT_MainECCLock(1)          |       \
        sNFCONT_InitECC(0)                      |       \
        sNFCONT_Reg_nCE(1)                      |       \
        sNFCONT_LoadPageSize(0)         |       \
        sNFCONT_Lock_tight(0)           |       \
        sNFCONT_Lock(0)                         |       \
        sNFCONT_Mode(3)                                 \
)
                                                                                                                             
#define elfin_nand_init_controller()                                                    \
do{ NFCONF = ( (NFCONF & NFCONF_KeepMask) | NFCONF_InitSet );   \
        NFCONT = NFCONT_InitSet;                                                                        \
        printk("NFCONF:[0x%08x] NFCONT:[0x%08x] NFSTAT:[0x%08x]\n",NFCONF,NFCONT,NFSTAT); }while(0)
                                                                                                                             
#define elfin_nand_select()                     do{ NFCONT &= m0NFCONT_Reg_nCE; }while(0)
#define elfin_nand_deselect()           do{ NFCONT |= m1NFCONT_Reg_nCE; }while(0)
                                                                                                                             
#define elfin_nand_put_cmd(cmd)         do{ NFCMMD = sNFCMMD_NFCMMD0(cmd); }while(0)
#define elfin_nand_put_addr(addr)       do{ NFADDR = sNFADDR_NFADDR0(addr); }while(0)
#define elfin_nand_put_data(data)       do{ NFDATA = sNFDATA_NFDATA0(data); }while(0)
#define elfin_nand_get_data()           ((u_char)(NFDATA & m1NFDATA_NFDATA0))
                                                                                                                             
#define elfin_nand_clear_RnB()          do{ NFSTAT |= m1NFSTAT_RnB_TransDetect; }while(0)
#define elfin_nand_ready_flag()         ((NFSTAT & m1NFSTAT_Flash_RnB0) ? 1 : 0)


/* 
 *	hardware specific access to control-lines
*/
static void s3csmc_hwcontrol(struct mtd_info *mtd, int cmd)
{

	switch(cmd){

		case NAND_CTL_SETCLE: 
			printk("NAND_CTL_SETCLE\r\n");
			break;
		case NAND_CTL_CLRCLE:
			printk("NAND_CTL_CLRCLE\r\n");
			break;
		case NAND_CTL_SETALE:
			printk("NAND_CTL_SETALE\r\n");
			break;
		case NAND_CTL_CLRALE: 
			printk("NAND_CTL_CLRALE\r\n");
			break;
		case NAND_CTL_SETNCE:
			elfin_nand_select();
			break;
		case NAND_CTL_CLRNCE:
			elfin_nand_deselect();
			break;
		case NAND_CTL_SETWP:
			printk("NAND_CTL_SETWP\r\n");
			break;
		case NAND_CTL_CLRWP:
			printk("NAND_CTL_CLRWP\r\n");
			break;
	}
}

/*
*	read device ready pin
*/
static int s3csmc_device_ready(struct mtd_info *mtd)
{
	int ready;
	ready =  elfin_nand_ready_flag();
	return ready;
}
void s3csmc_enable_hwecc(struct mtd_info *mtd, int mode)
{
}
static void s3csmc_disable_ecc(void)
{
}
static void s3csmc_enable_read_ecc(void)
{