nwatadrv.h

ks8695的ide硬盘程序

/* ataDrv.h - ATA/IDE (LOCAL and PCMCIA) disk controller header */

/* Copyright 1984-1996 Wind River Systems, Inc. */
/*
modification history
--------------------
2005-11-19 10:27   YOUYAN 根据《dvs7004相关功能接口（2005-10-28）
                   改写数据结构和增加接口函数定义
*/

#ifndef INC_NWATADRV_H
#define INC_NWATADRV_H

#ifdef __cplusplus
extern "C" {
#endif

#ifndef _ASMLANGUAGE

#include "pccardLib.h"
#include "../Vxworks2Linux/Vxworks2Linux.h"

IMPORT ATA_RESOURCE ataResources[];
/* define swap macro for little/big endian machines */

#if _BYTE_ORDER == _BIG_ENDIAN
#   define ATA_SWAP(x) LONGSWAP(x)
#else
#   define ATA_SWAP(x) (x)
#endif

/* add by wangb 2005-10-18 13:59 */
#define PCI_LAT_TIMER          0x40            /* latency timer value, 64 PCI clocks */
#undef  ATA_CACHE_SIZE
#define ATA_CACHE_SIZE (128*1024)
#define	INCLUDE_ATA_HD
/* end by wangb 2005-10-18 14:00 */
#define IDE_LOCAL		0 	/* ctrl type: LOCAL(IDE) */
#define ATA_PCMCIA		1	/* ctrl type: PCMCIA */

#define ATA_MAX_CTRLS		1	/* max number of ATA controller */
#define ATA_MAX_DRIVES		2	/* max number of ATA drives */

#define ATA_ATP86X_VENID   0x1191		/* IDE Chip ATP86X VENDOR_ID */

#define ATA_ATP865_DEVID1  0x0008
#define ATA_ATP865_DEVID2  0x0009
#define ATA_ATP867_DEVID1  0x000A

#define ATA_ATP86X_PCI_CFG_            0x43

#define IDE_CNTRLR0_INT_LVL	0x0e	/* ATA/EIDE cntrlr 0 interrupt level */
#define IDE_CNTRLR1_INT_LVL	0x0f	/* ATA/EIDE cntrlr 1 interrupt level */
#define CPU_PCI_ISA_IO_ADRS 0x80000000      /* base of ISA I/O space */

typedef struct ataParams 
    {
    unsigned short config;		/* general configuration */
    unsigned short cylinders;		/* number of cylinders */
    unsigned short removcyl;		/* number of removable cylinders */
    unsigned short heads;		/* number of heads */
    unsigned short bytesTrack;		/* number of unformatted bytes/track */
    unsigned short bytesSec;		/* number of unformatted bytes/sector */
    unsigned short sectors;		/* number of sectors/track */
    unsigned short bytesGap;		/* minimum bytes in intersector gap */
    unsigned short bytesSync;		/* minimum bytes in sync field */
    unsigned short vendstat;		/* number of unsigned shorts of vendor status */
    char serial[20];		/* controller serial number */
    unsigned short type;			/* controller type */
    unsigned short size;			/* sector buffer size, in sectors */
    unsigned short bytesEcc;		/* ecc bytes appended */
    char rev[8];		/* firmware revision */
    char model[40];		/* model name */
    unsigned short multiSecs;		/* RW multiple support. bits 7-0 ia max secs */
    unsigned short reserved48;		/* reserved */
    unsigned short capabilities;		/* capabilities */
    unsigned short reserved50;		/* reserved */
    unsigned short pioMode;		/* PIO data transfer cycle timing mode */
    unsigned short dmaMode;		/* single unsigned short DMA data transfer cycle timing */
    unsigned short valid;		/* field validity */
    unsigned short currentCylinders;	/* number of current logical cylinders */
    unsigned short currentHeads;		/* number of current logical heads */
    unsigned short currentSectors;	/* number of current logical sectors / track */
    unsigned short capacity0;		/* current capacity in sectors */
    unsigned short capacity1;		/* current capacity in sectors */
    unsigned short multiSet;		/* multiple sector setting */
    unsigned short sectors0;		/* total number of user addressable sectors */
    unsigned short sectors1;		/* total number of user addressable sectors */
    unsigned short singleDma;		/* obsolete */
    unsigned short multiDma;		    /* multi unsigned short DMA transfer */
    unsigned short advancedPio;		/* flow control PIO transfer modes supported */
    unsigned short cycletimeDma;		/* minimum multiunsigned short DMA transfer cycle time */
    unsigned short cycletimeMulti;	/* recommended multiunsigned short DMA cycle time */
    unsigned short cycletimePioNoIordy;	/* min PIO transfer cycle time wo flow ctl */
    unsigned short cycletimePioIordy;	/* min PIO transfer cycle time w IORDY */
    unsigned short reserved71[17];   /* reserved */
   	unsigned short feature;				/* 48-bit support							*/
    unsigned short ultraDma;         /* ultra DMA transfer */
	unsigned short reserved12[12];    
	unsigned short sectorsExt0;		    /* total number of user addressable sectors Ext */
	unsigned short sectorsExt1;		    /* total number of user addressable sectors Ext */
	unsigned short sectorsExt2;		    /* total number of user addressable sectors Ext */
	unsigned short sectorsExt3;		    /* total number of user addressable sectors Ext */

    unsigned short reserved24[24];
    unsigned short vendor[32];		/* vendor specific */
    unsigned short reserved160[96];	/* reserved */
    } ATA_PARAM;

typedef struct ataDrive
    {
    ATA_PARAM	param;		/* geometry parameter */
    short	okMulti;	/* MULTI: TRUE if supported */
    short	okIordy;	/* IORDY: TRUE if supported */
    short	okDma;		/* DMA:   TRUE if supported */
    short	okLba;		/* LBA:   TRUE if supported */
    short	multiSecs;	/* supported max sectors for multiple RW */
    short	pioMode;	/* supported max PIO mode */
    short	ultraDmaMode;	/* supported ultra word DMA mode */
    short	multiDmaMode;	/* supported max multi word DMA mode */
    short	rwMode;		/* RW mode: PIO[0,1,2,3,4] or DMA[0,1,2] */
    short	rwBits;		/* RW bits: 16 or 32 */
    short	rwPio;		/* RW PIO unit: single or multi sector */
    short	rwDma;		/* RW DMA unit: single or multi word */
    short lba48bit;		/* 48-bit address or 28-bit address   add by wb 2005-6-20 13:30 */
    short status;  /*ide 工作模式， 0=standby, 1=active added by youyan 2005-11-19 10:27 */
    } ATA_DRIVE;

typedef struct ataCtrl
    {
    ATA_DRIVE	drive[ATA_MAX_DRIVES];	/* drives per controller */
    SEM_ID	syncSem;	/* binary sem for syncronization */
    SEM_ID	muteSem;	/* mutex  sem for mutual-exclusion */
    WDOG_ID	wdgId;		/* watch dog */
    BOOL	wdgOkay;	/* watch dog status */
    int		semTimeout;	/* timeout seconds for sync semaphore */
    int		wdgTimeout;	/* timeout seconds for watch dog */
    int		ctrlType;	/* type of controller */
    BOOL	installed;	/* TRUE if a driver is installed */
    BOOL	changed;	/* TRUE if a card is installed */
    int		intLevel;	/* interrupt level */
    int		intCount;	/* interrupt count */
    int		intStatus;	/* interrupt status */
    int		drives;		/* number of drives in the controller */
    UINT32	data;		/* (RW) data register (16 bits)	*/
    UINT32	error;		/* (R)  error register		*/
    UINT32	feature;	/* (W)  feature or write-precompensation */
    UINT32	seccnt;		/* (RW) sector count		*/
    UINT32	sector;		/* (RW) first sector number	*/
    UINT32	cylLo;		/* (RW) cylinder low byte	*/
    UINT32	cylHi;		/* (RW) cylinder high byte	*/
    UINT32	sdh;		/* (RW) sector size/drive/head	*/
    UINT32	command;	/* (W)  command register	*/
    UINT32	status;		/* (R)  immediate status	*/
    UINT32	aStatus;	/* (R)  alternate status	*/
    UINT32	dControl;	/* (W)  disk controller control	*/
    UINT32	dAddress;	/* (R)  disk controller address */
    } ATA_CTRL;

typedef struct ataDev
    {
    BLK_DEV blkDev;		/* must be here */
    int ctrl;			/* ctrl no.  0 - 1 */
    int drive;			/* drive no. 0 - 1 */
    int blkOffset;		/* sector offset */
    } ATA_DEV;

typedef struct ataType
    {
    int cylinders;		/* number of cylinders */
    int heads;			/* number of heads */
    int sectors;		/* number of sectors per track */
    int bytes;			/* number of bytes per sector */
    int precomp;		/* precompensation cylinder */
    } ATA_TYPE;

typedef struct ataRaw
    {				/* this is for ATARAWACCESS ioctl */
    UINT cylinder;		/* cylinder (0 -> (cylindres-1)) */
    UINT head;			/* head (0 -> (heads-1)) */
    UINT sector;		/* sector (1 -> sectorsTrack) */
    char *pBuf;			/* pointer to buffer (bytesSector * nSecs) */
    UINT nSecs;			/* number of sectors (1 -> sectorsTrack) */
    UINT direction;		/* read=0, write=1 */
    } ATA_RAW;


#define ATA_SEM_TIMEOUT_DEF	1       /* default timeout for ATA sync sem */
#define ATA_WDG_TIMEOUT_DEF	2       /* default timeout for ATA watch dog 5-->2  */


/* ATA registers */

#define	ATA_DATA(base0)		(base0 + 0) /* (RW) data register (16 bits) */
#define ATA_ERROR(base0)	(base0 + 1) /* (R)  error register	    */
#define	ATA_FEATURE(base0)	(base0 + 1) /* (W)  feature/precompensation */
#define	ATA_SECCNT(base0)	(base0 + 2) /* (RW) sector count	    */
#define	ATA_SECTOR(base0)	(base0 + 3) /* (RW) first sector number	    */
#define	ATA_CYL_LO(base0)	(base0 + 4) /* (RW) cylinder low byte	    */
#define	ATA_CYL_HI(base0)	(base0 + 5) /* (RW) cylinder high byte	    */
#define	ATA_SDH(base0)		(base0 + 6) /* (RW) sector size/drive/head  */
#define	ATA_COMMAND(base0)	(base0 + 7) /* (W)  command register	    */
#define	ATA_STATUS(base0) 	(base0 + 7) /* (R)  immediate status	    */
#define	ATA_A_STATUS(base1)	(base1 + 0) /* (R)  alternate status	    */
#define	ATA_D_CONTROL(base1) (base1 + 0) /* (W)  disk controller control */
#define	ATA_D_ADDRESS(base1) (base1 + 1) /* (R)  disk controller address */