📄 davincievm_arm.gel
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* *
* pll_multiplier <- 16: Normal mode ( For PLL1 ) *
* 21: Turbo mode *
* *
* pll_divider1 <- Divider #1 ( For PLL2 ) *
* *
* pll_divider2 <- Divider #2 ( For PLL2 ) *
* *
* ------------------------------------------------------------------------ */
setup_pll_on( unsigned int pll_number, unsigned int clock_source,
unsigned int pll_multipler, unsigned int pll_divider1,
unsigned int pll_divider2 )
{
#define PLL1_BASE 0x01C40800
#define PLL1_PLLCTL ( PLL1_BASE + 0x100 ) // PLL Control
#define PLL1_PLLM ( PLL1_BASE + 0x110 ) // PLL Multiplier
#define PLL2_BASE 0x01C40C00
#define PLL2_PLLCTL ( PLL2_BASE + 0x100 ) // PLL Control
#define PLL2_PLLM ( PLL2_BASE + 0x110 ) // PLL Multiplier
#define PLL2_PLLDIV1 ( PLL2_BASE + 0x118 ) // PLL Div1
#define PLL2_PLLDIV2 ( PLL2_BASE + 0x11C ) // PLL Div2
#define PLL2_PLLCMD ( PLL2_BASE + 0x138 ) // PLL Command
#define PLL2_PLLSTAT ( PLL2_BASE + 0x13C ) // PLL Status
unsigned int* pll_ctl;
unsigned int* pll_pllm;
unsigned int* pll_div1;
unsigned int* pll_div2;
unsigned int* pll_cmd;
unsigned int* pll_stat;
if ( pll_number == 1 )
{
pll_ctl = ( unsigned int* )PLL1_PLLCTL;
pll_pllm = ( unsigned int* )PLL1_PLLM;
}
else
{
pll_ctl = ( unsigned int* )PLL2_PLLCTL;
pll_pllm = ( unsigned int* )PLL2_PLLM;
pll_div1 = ( unsigned int* )PLL2_PLLDIV1;
pll_div2 = ( unsigned int* )PLL2_PLLDIV2;
pll_cmd = ( unsigned int* )PLL2_PLLCMD;
pll_stat = ( unsigned int* )PLL2_PLLSTAT;
}
*pll_ctl &= 0xFFFFFEFF; // Clear clock source mode
*pll_ctl |= ( clock_source << 8 ); // Set clock source mode
*pll_ctl &= 0xFFFFFFDE; // Set PLL to Bypass mode
sw_wait( 0x20 ); // Wait Bypass mode switch
*pll_ctl &= 0xFFFFFFF7; // Reset PLL
*pll_ctl |= 0x00000010; // Disable PLL
*pll_ctl &= 0xFFFFFFFD; // Power up PLL
*pll_ctl &= 0xFFFFFFEF; // Enable PLL
*pll_pllm = pll_multipler; // Set PLL multipler
/*
* For PLL1: DSP, ARM, VBUS, ImCop, CFG are fixed
*
* For PLL2: DDR2 and VPBE are programmable
*/
if ( pll_number != 1 )
{
*pll_div1 = pll_divider1; // Set PLL dividers
*pll_div2 = pll_divider2;
*pll_div1 |= 0x00008000; // Enable PLL dividers
*pll_div2 |= 0x00008000;
*pll_cmd |= 0x00000001; // Set phase alignment
while( ( pll_stat & 1 ) == 1 ){}// Wait for operation to finish
}
sw_wait( 0x100 ); // Wait for PLL to Reset
*pll_ctl |= 0x00000008; // Release PLL from Reset
sw_wait( 0x1000 ); // Wait for PLL to LOCK
*pll_ctl |= 0x00000001; // Set PLL to PLL mode
}
/* ------------------------------------------------------------------------ *
* *
* setup_pll_1( ) *
* *
* Setup PLL1 *
* *
* clock_source <- 0: Onchip Oscillator *
* 1: External Oscillator *
* *
* pll_multiplier <- 16: Normal mode ( For PLL1 ) *
* 21: Turbo mode *
* *
* ------------------------------------------------------------------------ */
setup_pll_1( int clock_source, int pll_multiplier )
{
setup_pll_on( 1, clock_source, pll_multiplier, 0, 0 );
if ( ( pll_multiplier == 16 ) && ( clock_source == 0 ) )
GEL_TextOut( "PLL1 started ( Normal Mode @ 459 MHz ) w/ Crystal Oscilator\n" );
else if ( ( pll_multiplier == 21 ) && ( clock_source == 0 ) )
GEL_TextOut( "PLL1 started ( Turbo Mode @ 594 MHz ) w/ Crystal Oscilator\n" );
else if ( ( pll_multiplier == 16 ) && ( clock_source == 1 ) )
GEL_TextOut( "PLL1 started ( Normal Mode @ 459 MHz ) w/ External Clock\n" );
else if ( ( pll_multiplier == 21 ) && ( clock_source == 1 ) )
GEL_TextOut( "PLL1 started ( Turbo Mode @ 594 MHz ) w/ External Clock\n" );
}
/* ------------------------------------------------------------------------ *
* *
* setup_pll_2( ) *
* *
* Setup PLL2 *
* *
* clock_source <- 0: Onchip Oscillator *
* 1: External Oscillator *
* *
* pll_multiplier <- X *
* *
* pll_divider1 <- VPSS divider ( For PLL2 ) *
* *
* pll_divider2 <- DDR2 divider ( For PLL2 ) *
* *
* ------------------------------------------------------------------------ */
setup_pll_2( int clock_source, int pll_multiplier, int vpss_divider, int ddr2_divider )
{
setup_pll_on( 2, clock_source, pll_multiplier, vpss_divider, ddr2_divider );
if ( ( pll_multiplier == 19 ) && ( ddr2_divider == 1 ) && ( clock_source == 0 ) )
GEL_TextOut( "PLL2 started ( DDR2 @ 135 MHz ) w/ Crystal Oscilator\n" );
else if ( ( pll_multiplier == 19 ) && ( ddr2_divider == 1 ) && ( clock_source == 1 ) )
GEL_TextOut( "PLL2 started ( DDR2 @ 135 MHz ) w/ External Clock\n" );
else if ( ( pll_multiplier == 27 ) && ( ddr2_divider == 2 ) && ( clock_source == 0 ) )
GEL_TextOut( "PLL2 started ( DDR2 @ 126 MHz ) w/ Crystal Oscilator\n" );
else if ( ( pll_multiplier == 27 ) && ( ddr2_divider == 2 ) && ( clock_source == 1 ) )
GEL_TextOut( "PLL2 started ( DDR2 @ 126 MHz ) w/ External Clock\n" );
}
/* ------------------------------------------------------------------------ *
* *
* setup_psc_on( ) *
* *
* Setup the PSC *
* *
* ------------------------------------------------------------------------ */
setup_psc_on( int domain, int id )
{
#define PSC_BASE 0x01C41000
#define PSC_EPCPR *( unsigned int* )( 0x01C41070 )
#define PSC_PTCMD *( unsigned int* )( 0x01C41120 )
#define PSC_PTSTAT *( unsigned int* )( 0x01C41128 )
#define PSC_PDSTAT0 *( unsigned int* )( 0x01C41200 )
#define PSC_PDSTAT1 *( unsigned int* )( 0x01C41204 )
#define PSC_PDCTL0 *( unsigned int* )( 0x01C41300 )
#define PSC_PDCTL1 *( unsigned int* )( 0x01C41304 )
#define PSC_EPCCR *( unsigned int* )( 0x01C41078 )
#define PSC_MDSTAT_BASE ( 0x01C41800 )
#define PSC_MDCTL_BASE ( 0x01C41A00 )
unsigned int* mdstat = ( unsigned int* )( PSC_MDSTAT_BASE + 4 * id );
unsigned int* mdctl = ( unsigned int* )( PSC_MDCTL_BASE + 4 * id );
unsigned int domainbit = ( 1 << domain ); // ALWAYSON or DSP domain
*mdctl &= ~0x001F; // Clear next module state
*mdctl |= 0x0003; // Set next module state to enable
if ( ( id == 1 )
|| ( ( id >= 5 ) && ( id <= 7 ) )
|| ( ( id >= 9 ) && ( id <= 17 ) )
|| ( id == 26 )
|| ( id == 40 ) )
*mdctl |= 0x0203; // Set EMURSTIE to 0x1
if ( ( PSC_PDSTAT0 & 1 ) == 0 ) // Check if PSC is OFF
{
PSC_PDCTL1 |= 0x0001; // Turn ON power domain
PSC_PTCMD = domainbit; // Start power state transition
while ( ( PSC_EPCPR & domainbit ) == 0 ); // Wait for external power request
PSC_PDCTL1 |= 0x0100; // Turn ON external power
while( ( PSC_PTSTAT & domainbit ) != 0 ); // Wait for power state transtion to finish
}
else // Check if PSC is ON
{
PSC_PTCMD = domainbit; // Start power state transition
while( ( PSC_PTSTAT & domainbit ) != 0 ); // Wait for power state transtion to finish
}
while( ( *mdstat & 0x001F ) != 0x3 ); // Wait for module state enable
}
/* ------------------------------------------------------------------------ *
* *
* setup_psc_all_on( ) *
* *
* Enable all PSC modules on ALWAYSON and DSP power dominas. *
* *
* ------------------------------------------------------------------------ */
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