pxa_camera.h

pxa270下的摄像头mtd91111的驱动

/*
 *  pxa_camera.h
 *
 *  Bulverde Processor Camera Interface driver header.
 *
 *  Copyright (C) 2003, Intel Corporation
 *  Copyright (C) 2003, Montavista Software Inc.
 *
 *  Author: Intel Corporation Inc.
 *          MontaVista Software, Inc.
 *           [e-mail]
 * 
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 */

#ifndef __PXA_CAMERA_H__
#define __PXA_CAMERA_H__

#define WCAM_VIDIOCSCAMREG  	211
#define WCAM_VIDIOCGCAMREG   	212
#define WCAM_VIDIOCSCIREG    	213
#define WCAM_VIDIOCGCIREG    	214
#define WCAM_VIDIOCSINFOR	215
#define WCAM_VIDIOCGINFOR	216 
#define WCAM_VIDIOCGCAPINFO	217 

/*
Image format definition
*/
#define CAMERA_IMAGE_FORMAT_RAW8                0
#define CAMERA_IMAGE_FORMAT_RAW9                1
#define CAMERA_IMAGE_FORMAT_RAW10               2
                                                                                                                             
#define CAMERA_IMAGE_FORMAT_RGB444              3
#define CAMERA_IMAGE_FORMAT_RGB555              4
#define CAMERA_IMAGE_FORMAT_RGB565              5
#define CAMERA_IMAGE_FORMAT_RGB666_PACKED       6
#define CAMERA_IMAGE_FORMAT_RGB666_PLANAR       7
#define CAMERA_IMAGE_FORMAT_RGB888_PACKED       8
#define CAMERA_IMAGE_FORMAT_RGB888_PLANAR       9
#define CAMERA_IMAGE_FORMAT_RGBT555_0          10  //RGB+Transparent bit 0
#define CAMERA_IMAGE_FORMAT_RGBT888_0          11
#define CAMERA_IMAGE_FORMAT_RGBT555_1          12  //RGB+Transparent bit 1
#define CAMERA_IMAGE_FORMAT_RGBT888_1          13
                                                                                                                             
#define CAMERA_IMAGE_FORMAT_YCBCR400           14
#define CAMERA_IMAGE_FORMAT_YCBCR422_PACKED    15
#define CAMERA_IMAGE_FORMAT_YCBCR422_PLANAR    16
#define CAMERA_IMAGE_FORMAT_YCBCR444_PACKED    17
#define CAMERA_IMAGE_FORMAT_YCBCR444_PLANAR    18
//#define CAMERA_IMAGE_FORMAT_YCBCR420_PLANAR	   19	yul added @2006-1-12 10:45


/*
Bpp definition
*/

#define YUV422_BPP				16
#define RGB565_BPP				16
#define RGB666_UNPACKED_BPP			32
#define RGB666_PACKED_BPP			24

/*
VIDIOCCAPTURE Arguments
*/
#define STILL_IMAGE				1
#define VIDEO_START				0
#define VIDEO_STOP				-1


#define VID_HARDWARE_PXA_CAMERA 	50 /* subject to change */

#define STATUS_FAILURE	(0)
#define STATUS_SUCCESS	(1)
#define STATUS_WRONG_PARAMETER  -1

/*
 * Macros
 */

/*
 * Sensor type
 */
#define CAMERA_TYPE_ADCM_2650               01
#define CAMERA_TYPE_ADCM_2670               02
#define CAMERA_TYPE_ADCM_2700               03
#define CAMERA_TYPE_OMNIVISION_9640         04
#define CAMERA_TYPE_MAX                     CAMERA_TYPE_OMNIVISION_9640

/*
 * Image format definition
 */
#define CAMERA_IMAGE_FORMAT_MAX               CAMERA_IMAGE_FORMAT_YCBCR444_PLANAR /*yul   CAMERA_IMAGE_FORMAT_YCBCR420_PLANAR*/

/* Interrupt mask */
#define CAMERA_INTMASK_FIFO_OVERRUN            0x0001
#define CAMERA_INTMASK_END_OF_FRAME            0x0002  
#define CAMERA_INTMASK_START_OF_FRAME          0x0004
#define CAMERA_INTMASK_CI_DISABLE_DONE         0x0008
#define CAMERA_INTMASK_CI_QUICK_DISABLE        0x0010
#define CAMERA_INTMASK_PARITY_ERROR            0x0020
#define CAMERA_INTMASK_END_OF_LINE             0x0040
#define CAMERA_INTMASK_FIFO_EMPTY              0x0080
#define CAMERA_INTMASK_RCV_DATA_AVALIBLE       0x0100
#define CAMERA_INTMASK_TIME_OUT                0x0200
#define CAMERA_INTMASK_END_OF_DMA              0x0400

/* Interrupt status */
#define CAMERA_INTSTATUS_FIFO_OVERRUN_0        0x00000001
#define CAMERA_INTSTATUS_FIFO_OVERRUN_1        0x00000002
#define CAMERA_INTSTATUS_FIFO_OVERRUN_2        0x00000004
#define CAMERA_INTSTATUS_END_OF_FRAME          0x00000008  
#define CAMERA_INTSTATUS_START_OF_FRAME        0x00000010
#define CAMERA_INTSTATUS_CI_DISABLE_DONE       0x00000020
#define CAMERA_INTSTATUS_CI_QUICK_DISABLE      0x00000040
#define CAMERA_INTSTATUS_PARITY_ERROR          0x00000080
#define CAMERA_INTSTATUS_END_OF_LINE           0x00000100
#define CAMERA_INTSTATUS_FIFO_EMPTY_0          0x00000200
#define CAMERA_INTSTATUS_FIFO_EMPTY_1          0x00000400
#define CAMERA_INTSTATUS_FIFO_EMPTY_2          0x00000800
#define CAMERA_INTSTATUS_RCV_DATA_AVALIBLE_0   0x00001000
#define CAMERA_INTSTATUS_RCV_DATA_AVALIBLE_1   0x00002000
#define CAMERA_INTSTATUS_RCV_DATA_AVALIBLE_2   0x00004000
#define CAMERA_INTSTATUS_TIME_OUT              0x00008000
#define CAMERA_INTSTATUS_END_OF_DMA            0x00010000

/* Capture status */
#define CAMERA_STATUS_VIDEO_CAPTURE_IN_PROCESS 0x0001
#define CAMERA_STATUS_RING_BUFFER_FULL         0x0002

/*
 * Camera Interface Register definitions
 */

enum CI_REGBITS_CICR0 {
        CI_CICR0_FOM       = 0x00000001,
        CI_CICR0_EOFM      = 0x00000002,
        CI_CICR0_SOFM      = 0x00000004,
        CI_CICR0_CDM       = 0x00000008,
        CI_CICR0_QDM       = 0x00000010,
        CI_CICR0_PERRM     = 0x00000020,
        CI_CICR0_EOLM      = 0x00000040,
        CI_CICR0_FEM       = 0x00000080,
        CI_CICR0_RDAVM     = 0x00000100,
        CI_CICR0_TOM       = 0x00000200,
        CI_CICR0_RESERVED  = 0x03FFFC00,
        CI_CICR0_SIM_SHIFT = 24,
        CI_CICR0_SIM_SMASK = 0x7,
        CI_CICR0_DIS       = 0x08000000,
        CI_CICR0_ENB       = 0x10000000,
        CI_CICR0_SL_CAP_EN = 0x20000000,
        CI_CICR0_PAR_EN    = 0x40000000,
        CI_CICR0_DMA_EN    = 0x80000000,
        CI_CICR0_INTERRUPT_MASK = 0x3FF
};

enum CI_REGBITS_CICR1 {
	CI_CICR1_DW_SHIFT   		= 0,
	CI_CICR1_DW_SMASK   		= 0x7,
	CI_CICR1_COLOR_SP_SHIFT 	= 3,
	CI_CICR1_COLOR_SP_SMASK 	= 0x3,
	CI_CICR1_RAW_BPP_SHIFT  	= 5,
	CI_CICR1_RAW_BPP_SMASK  	= 0x3,
	CI_CICR1_RGB_BPP_SHIFT  	= 7,
	CI_CICR1_RGB_BPP_SMASK  	= 0x7,
	CI_CICR1_YCBCR_F		= 0x00000400,
	CI_CICR1_RBG_F  		= 0x00000800,
	CI_CICR1_RGB_CONV_SHIFT 	= 12,
	CI_CICR1_RGB_CONV_SMASK 	= 0x7,
	CI_CICR1_PPL_SHIFT  		= 15,
	CI_CICR1_PPL_SMASK  		= 0x7FF,
	CI_CICR1_RESERVED   		= 0x1C000000,
	CI_CICR1_RGBT_CONV_SHIFT	= 29,
	CI_CICR1_RGBT_CONV_SMASK	= 0x3,
	CI_CICR1_TBIT   		= 0x80000000
};

enum CI_REGBITS_CICR2 {
	CI_CICR2_FSW_SHIFT 	= 0,
	CI_CICR2_FSW_SMASK 	= 0x3,
	CI_CICR2_BFPW_SHIFT	= 3,
	CI_CICR2_BFPW_SMASK	= 0x3F,
	CI_CICR2_RESERVED  	= 0x00000200,
	CI_CICR2_HSW_SHIFT 	= 10,
	CI_CICR2_HSW_SMASK 	= 0x3F,
	CI_CICR2_ELW_SHIFT 	= 16,
	CI_CICR2_ELW_SMASK 	= 0xFF,
	CI_CICR2_BLW_SHIFT 	= 24,
	CI_CICR2_BLW_SMASK 	= 0xFF    
};

enum CI_REGBITS_CICR3 {
	CI_CICR3_LPF_SHIFT 	= 0,
	CI_CICR3_LPF_SMASK 	= 0x7FF,
	CI_CICR3_VSW_SHIFT 	= 11,
	CI_CICR3_VSW_SMASK 	= 0x1F,
	CI_CICR3_EFW_SHIFT 	= 16,
	CI_CICR3_EFW_SMASK 	= 0xFF,
	CI_CICR3_BFW_SHIFT 	= 24,
	CI_CICR3_BFW_SMASK 	= 0xFF
};

enum CI_REGBITS_CICR4 {
	CI_CICR4_DIV_SHIFT 	= 0,
	CI_CICR4_DIV_SMASK 	= 0xFF,
	CI_CICR4_FR_RATE_SHIFT 	= 8,
	CI_CICR4_FR_RATE_SMASK 	= 0x7,
	CI_CICR4_RESERVED1 	= 0x0007F800,
	CI_CICR4_MCLK_EN   	= 0x00080000,
	CI_CICR4_VSP   		= 0x00100000,
	CI_CICR4_HSP   		= 0x00200000,
	CI_CICR4_PCP   		= 0x00400000,
	CI_CICR4_PCLK_EN   	= 0x00800000,
	CI_CICR4_RESERVED2 	= 0xFF000000,
	CI_CICR4_RESERVED  	= CI_CICR4_RESERVED1 | CI_CICR4_RESERVED2
};

enum CI_REGBITS_CISR {
	CI_CISR_IFO_0  		= 0x00000001,
	CI_CISR_IFO_1  		= 0x00000002,
	CI_CISR_IFO_2  		= 0x00000004,
	CI_CISR_EOF		= 0x00000008,
	CI_CISR_SOF		= 0x00000010,
	CI_CISR_CDD		= 0x00000020,
	CI_CISR_CQD		= 0x00000040,
	CI_CISR_PAR_ERR		= 0x00000080,
	CI_CISR_EOL		= 0x00000100,
	CI_CISR_FEMPTY_0   	= 0x00000200,
	CI_CISR_FEMPTY_1   	= 0x00000400,
	CI_CISR_FEMPTY_2   	= 0x00000800,
	CI_CISR_RDAV_0 		= 0x00001000,
	CI_CISR_RDAV_1 		= 0x00002000,
	CI_CISR_RDAV_2 		= 0x00004000, 
	CI_CISR_FTO		= 0x00008000,
	CI_CISR_RESERVED   	= 0xFFFF0000
};

enum CI_REGBITS_CIFR {
	CI_CIFR_FEN0   		= 0x00000001,
	CI_CIFR_FEN1   		= 0x00000002,
	CI_CIFR_FEN2   		= 0x00000004,
	CI_CIFR_RESETF 		= 0x00000008,
	CI_CIFR_THL_0_SHIFT	= 4,
	CI_CIFR_THL_0_SMASK	= 0x3,
	CI_CIFR_RESERVED1  	= 0x000000C0,
	CI_CIFR_FLVL0_SHIFT	= 8,
	CI_CIFR_FLVL0_SMASK	= 0xFF,
	CI_CIFR_FLVL1_SHIFT	= 16,
	CI_CIFR_FLVL1_SMASK	= 0x7F,
	CI_CIFR_FLVL2_SHIFT	= 23,
	CI_CIFR_FLVL2_SMASK	= 0x7F,
	CI_CIFR_RESERVED2  	= 0xC0000000,
	CI_CIFR_RESERVED   	= CI_CIFR_RESERVED1 | CI_CIFR_RESERVED2 
};

//---------------------------------------------------------------------------
//     Parameter Type definitions
//---------------------------------------------------------------------------
typedef enum  {
	CI_RAW8 = 0,		//RAW
	CI_RAW9,
	CI_RAW10,
	CI_YCBCR422,		//YCBCR
	CI_YCBCR422_PLANAR,	//YCBCR Planaried
	CI_RGB444,		//RGB
	CI_RGB555,
	CI_RGB565,
	CI_RGB666,
	CI_RGB888,
	CI_RGBT555_0,		//RGB+Transparent bit 0
	CI_RGBT888_0,
	CI_RGBT555_1,		//RGB+Transparent bit 1  
	CI_RGBT888_1,
	CI_RGB666_PACKED,	//RGB Packed 
	CI_RGB888_PACKED,
    /*CI_YCBCR420,               
    CI_YCBCR420_PLANAR,       added by yul @2006-1-12 10:04 */
	CI_INVALID_FORMAT = 0xFF
} CI_IMAGE_FORMAT;

typedef enum {
	CI_INTSTATUS_IFO_0  	= 0x00000001,
	CI_INTSTATUS_IFO_1  	= 0x00000002,
	CI_INTSTATUS_IFO_2  	= 0x00000004,
	CI_INTSTATUS_EOF	= 0x00000008,
	CI_INTSTATUS_SOF	= 0x00000010,
	CI_INTSTATUS_CDD	= 0x00000020,
	CI_INTSTATUS_CQD	= 0x00000040,
	CI_INTSTATUS_PAR_ERR	= 0x00000080,
	CI_INTSTATUS_EOL	= 0x00000100,
	CI_INTSTATUS_FEMPTY_0   = 0x00000200,
	CI_INTSTATUS_FEMPTY_1   = 0x00000400,
	CI_INTSTATUS_FEMPTY_2   = 0x00000800,
	CI_INTSTATUS_RDAV_0	= 0x00001000,
	CI_INTSTATUS_RDAV_1	= 0x00002000,
	CI_INTSTATUS_RDAV_2	= 0x00004000, 
	CI_INTSTATUS_FTO	= 0x00008000,
	CI_INTSTATUS_ALL	= 0x0000FFFF
} CI_INTERRUPT_STATUS;

typedef enum {
	CI_INT_IFO  	= 0x00000001,
	CI_INT_EOF  	= 0x00000002,
	CI_INT_SOF  	= 0x00000004,
	CI_INT_CDD  	= 0x00000008,