sdr_top.prf

使用FPGA做SDRAM控制器

#
# Logical Preferences generated for Lucent by Synplify 7.7.0, Build 053R.
#

# Period Constraints
FREQUENCY PORT "sys_CLK" 80.0 MHz;
# Output Constraints
CLOCK_TO_OUT "sys_REF_ACK" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sys_D_0" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sys_D_1" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sys_D_2" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sys_D_3" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sys_D_4" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sys_D_5" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sys_D_6" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sys_D_7" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sys_D_8" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sys_D_9" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sys_D_10" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sys_D_11" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sys_D_12" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sys_D_13" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sys_D_14" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sys_D_15" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sys_D_VALID" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sys_CYC_END" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sys_INIT_DONE" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_DQ_0" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_DQ_1" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_DQ_2" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_DQ_3" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_A_0" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_A_1" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_A_2" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_A_3" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_A_4" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_A_5" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_A_6" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_A_7" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_A_8" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_A_9" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_A_10" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_A_11" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_BA_0" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_BA_1" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_CKE" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_CSn" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_RASn" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_CASn" 12.5 NS CLKPORT = "sys_CLK";
CLOCK_TO_OUT "sdr_WEn" 12.5 NS CLKPORT = "sys_CLK";
# Input Constraints
INPUT_SETUP "sys_R_Wn" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_ADSn" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_DLY_100US" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_REF_REQ" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_0" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_1" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_2" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_3" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_4" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_5" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_6" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_7" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_8" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_9" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_10" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_11" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_12" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_13" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_14" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_15" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_16" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_17" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_18" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_19" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_20" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_21" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_A_22" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_D_0" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_D_1" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_D_2" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_D_3" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_D_4" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_D_5" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_D_6" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_D_7" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_D_8" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_D_9" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_D_10" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_D_11" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_D_12" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_D_13" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_D_14" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sys_D_15" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sdr_DQ_0" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sdr_DQ_1" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sdr_DQ_2" 12.5 NS CLKPORT = "sys_CLK";
INPUT_SETUP "sdr_DQ_3" 12.5 NS CLKPORT = "sys_CLK";

BLOCK ASYNCPATHS;

# End of generated Logical Preferences.