pci550x.h

linux下面

#define DA0_PACERL_WORK_R(d) (d = (readl(&REGS->r[0x0814]) >> 16))
#define DA0_PACERL_WORK_W(d) (writel(d << 16, &REGS->r[0x0814]))
#define DA0_PACERL_R(d) (d = (readl(&REGS->r[0x0815) >> 16))
#define DA0_PACERL_W(d) (writel(d << 16, &REGS->r[0x0815]))
#define DA0_PACERH_WORK_R(d) (d = (readl(&REGS->r[0x0816]) >> 16))
#define DA0_PACERH_WORK_W(d) (writel(d << 16, &REGS->r[0x0816]))
#define DA0_PACERH_R(d) (d = (readl(&REGS->r[0x0817]) >> 16))
#define DA0_PACERH_W(d) (writel(d << 16, &REGS->r[0x0817]))

#define DIO2_PACERL_WORK_R(d) ((u_int32_t)(d) = (REGS->r[0x0818]) & (MSW))
#define DIO2_PACERL_WORK_W(d) ((REGS->r[0x0818]) = (u_int32_t)(d) & (MSW))
#define DIO2_PACERL_R(d) ((u_int32_t)(d) = (REGS->r[0x0819) & (MSW))
#define DIO2_PACERL_W(d) ((REGS->r[0x0819]) = (u_int32_t)(d) & (MSW))
#define DIO2_PACERH_WORK_R(d) ((u_int32_t)(d) = (REGS->r[0x081A]) & (MSW))
#define DIO2_PACERH_WORK_W(d) ((REGS->r[0x081A]) = (u_int32_t)(d) & (MSW))
#define DIO2_PACERH_R(d) ((u_int32_t)(d) = (REGS->r[0x081B) & (MSW))
#define DIO2_PACERH_W(d) ((REGS->r[0x081B]) = (u_int32_t)(d) & (MSW))

#define DA1_PACERL_WORK_R(d) (d = (readl(&REGS->r[0x081C]) >> 16))
#define DA1_PACERL_WORK_W(d) (writel(d << 16, &REGS->r[0x081C]))
#define DA1_PACERL_R(d) (d = (readl(&REGS->r[0x081D) >> 16))
#define DA1_PACERL_W(d) (writel(d << 16, &REGS->r[0x081D]))
#define DA1_PACERH_WORK_R(d) (d = (readl(&REGS->r[0x081E]) >> 16))
#define DA1_PACERH_WORK_W(d) (writel(d << 16, &REGS->r[0x081E]))
#define DA1_PACERH_R(d) (d = (readl(&REGS->r[0x081F]) >> 16))
#define DA1_PACERH_W(d) (writel(d << 16, &REGS->r[0x081F]))

/* MEMORY POINTER, COUNTER, AND COUNTER WORK REGISTERS (R/W) */
#define AD_MPR0L_R(d) (d = readl(&REGS->r[0x0820]) >> 16)
#define AD_MPR0L_W(d) (writel(d << 16, &REGS->r[0x0820] ))
#define AD_MPR0H_R(d) (d = readl(&REGS->r[0x0821]) >> 16)
#define AD_MPR0H_W(d) (d = writel(d << 16, &REGS->r[0x0821]))
#define AD_MCR0_WORK_R(d) (d = readl(&REGS->r[0x0822]) >> 16)
#define AD_MCR0_WORK_W(d) (writel(d << 16, &REGS->r[0x0822]))
#define AD_MCR0_R(d) (d = readl(&REGS->r[0x0823]) >> 16)
#define AD_MCR0_W(d) (writel(d << 16, &REGS->r[0x0823]))
#define AD_MPR1L_R(d) (d = readl(&REGS->r[0x0824]) >> 16)
#define AD_MPR1L_W(d) (writel(d << 16, &REGS->r[0x0824]))
#define AD_MPR1H_R(d) (d = readl(&REGS->r[0x0825]) >> 16)
#define AD_MPR1H_W(d) (writel(d << 16, &REGS->r[0x0825]))
#define AD_MCR1_WORK_R(d) (d = (readl(&REGS->r[0x0826]) >> 16))
#define AD_MCR1_WORK_W(d) (writel(d << 16, &REGS->r[0x0826]))
#define AD_MCR1_R(d) (d = (readl(&REGS->r[0x0827]) >> 16))
#define AD_MCR1_W(d) (writel(d << 16, &REGS->r[0x0827]))

#define DA0_MPR0L_R(d) (d = readl(&REGS->r[0x0828]) >> 16)
#define DA0_MPR0L_W(d) (writel(d << 16, &REGS->r[0x0828] ))
#define DA0_MPR0H_R(d) (d = readl(&REGS->r[0x0829]) >> 16)
#define DA0_MPR0H_W(d) (writel(d << 16, &REGS->r[0x0829]))
#define DA0_MCR0_WORK_R(d) (d = readl(&REGS->r[0x082A]) >> 16)
#define DA0_MCR0_WORK_W(d) (writel(d << 16, &REGS->r[0x082A]))
#define DA0_MCR0_R(d)  (d = readl(&REGS->r[0x082B]) >> 16)
#define DA0_MCR0_W(d)  (writel(d << 16, &REGS->r[0x082B]))
#define DA0_MPR1L_R(d) (d = readl(&REGS->r[0x082C]) >> 16)
#define DA0_MPR1L_W(d) (writel(d << 16, &REGS->r[0x082C]))
#define DA0_MPR1H_R(d) (d = readl(&REGS->r[0x082D]) >> 16)
#define DA0_MPR1H_W(d) (writel(d << 16, &REGS->r[0x082D]))
#define DA0_MCR1_WORK_R(d) (d = readl(&REGS->r[0x082E]))
#define DA0_MCR1_WORK_W(d) (writel(d << 16, &REGS->r[0x082E]))
#define DA0_MCR1_R(d)  (d = readl(&REGS->r[0x082F]) >> 16)
#define DA0_MCR1_W(d)  (writel(d << 16, &REGS->r[0x082F]))

#define DIO2_MPR0L_R(d)   ((u_int32_t)(d) = (REGS->r[0x0830]) & (MSW))
#define DIO2_MCR0L_W(d) ((REGS->r[0x0830]) = (u_int32_t)(d) & (MSW))
#define DIO2_MPR0H_R(d)   ((u_int32_t)(d) = (REGS->r[0x0831]) & (MSW))
#define DIO2_MPR0H_W(d) ((REGS->r[0x0831]) = (u_int32_t)(d) & (MSW))
#define DIO2_MCR0_WORK_R(d)   ((u_int32_t)(d) = (REGS->r[0x0832]) & (MSW))
#define DIO2_MCR0_WORK_W(d) ((REGS->r[0x0832]) = (u_int32_t)(d) & (MSW))
#define DIO2_MCR0_R(d)   ((u_int32_t)(d) = (REGS->r[0x0833]) & (MSW))
#define DIO2_MCR0_W(d) ((REGS->r[0x0833]) = (u_int32_t)(d) & (MSW))
#define DIO2_MPR1L_R(d)   ((u_int32_t)(d) = (REGS->r[0x0834]) & (MSW))
#define DIO2_MCR1L_W(d) ((REGS->r[0x0834]) = (u_int32_t)(d) & (MSW))
#define DIO2_MPR1H_R(d)   ((u_int32_t)(d) = (REGS->r[0x0835]) & (MSW))
#define DIO2_MPR1H_W(d) ((REGS->r[0x0835]) = (u_int32_t)(d) & (MSW))
#define DIO2_MCR1_WORK_R(d)   ((u_int32_t)(d) = (REGS->r[0x0836]) & (MSW))
#define DIO2_MCR1_WORK_W(d) ((REGS->r[0x0836]) = (u_int32_t)(d) & (MSW))
#define DIO2_MCR1_R(d)   ((u_int32_t)(d) = (REGS->r[0x0837]) & (MSW))
#define DIO2_MCR1_W(d) ((REGS->r[0x0837]) = (u_int32_t)(d) & (MSW))

#define DA1_MPR0L_R(d) (d = readl(&REGS->r[0x0838]) >> 16)
#define DA1_MPR0L_W(d) (writel(d << 16, &REGS->r[0x0838]))
#define DA1_MPR0H_R(d) (d = readl(&REGS->r[0x0839]) >> 16)
#define DA1_MPR0H_W(d) (writel(d << 16, &REGS->r[0x0839]))
#define DA1_MCR0_WORK_R(d) (d = readl(&REGS->r[0x083A]) >> 16)
#define DA1_MCR0_WORK_W(d) (writel(d << 16, &REGS->r[0x083A]))
#define DA1_MCR0_R(d)  (d = readl(&REGS->r[0x083B]) >> 16)
#define DA1_MCR0_W(d)  (writel(d << 16, &REGS->r[0x083B]))
#define DA1_MPR1L_R(d) (d = readl(&REGS->r[0x083C]) >> 16)
#define DA1_MPR1L_W(d) (writel(d << 16, &REGS->r[0x083C]))
#define DA1_MPR1H_R(d) (d = readl(&REGS->r[0x083D]) >> 16)
#define DA1_MPR1H_W(d) (writel(d << 16, &REGS->r[0x083D]))
#define DA1_MCR1_WORK_R(d) (d = readl(&REGS->r[0x083E]) >> 16)
#define DA1_MCR1_WORK_W(d) (writel(d << 16, &REGS->r[0x083E]))
#define DA1_MCR1_R(d)  (d = readl(&REGS->r[0x083F]) >> 16)
#define DA1_MCR1_W(d)  (writel(d << 16, &REGS->r[0x083F]))

/* ADC CONVERSION COUNTER REGISTERS (32-Bit) (R/W) */
#define AD_CCOUNT_WORK_R(d) (d = (readl(&REGS->r[0x0802]) >> 16))
#define AD_CCOUNT_WORK_W(d) (writel(d << 16, &REGS->r[0x0802]))
#define AD_CCOUNT_R(d) (d = (readl(&REGS->r[0x0803]) >> 16))
#define AD_CCOUNT_W(d) (writel(d << 16, &REGS->r[0x0803]))

/* ADC BURST RATE REGISTERS (32-Bit) (R/W) */
#define AD_BRATE_WORK_R(d) (d = (readl(&REGS->r[0x0804]) >> 16))
#define AD_BRATE_WORK_W(d) (writel(d << 16, &REGS->r[0x0804]))
#define AD_BRATE_R(d) (d = (readl(&REGS->r[0x0805]) >> 16))
#define AD_BRATE_W(d) (writel(d << 16, &REGS->r[0x0805]))

/* ADC BURST LENGTH REGISTERS (32-Bit) (R/W) */
#define AD_BLENGTH_WORK_R(d) (d = (readl(&REGS->r[0x0806]) >> 16))
#define AD_BLENGTH_WORK_W(d) (writel(d << 16, &REGS->r[0x0806]))
#define AD_BLENGTH_R(d) ((u_int32_t)(d)) = ((REGS->r[0x0807]) >> 16)
#define AD_BLENGTH_W(d) ((REGS->r[0x0807])) = ((u_int32_t)(d) << 16)

/* -TIME DEPENDENT TIMER/COUNTER AND TIMER/COUNTER WORK REGISTERS- */
/* COUNTER0 WORK AND COUNTER0 REGISTERS (32-Bit) (R/W) */
#define CNTR0_WORK_R(d) (d = (readl(&REGS->r[0x0840]) >> 16))
#define CNTR0_WORK_W(d) (writel(d << 16, &REGS->r[0x0840]))
#define CNTR0_WORK_POLL(d) (d = (readl(&REGS->r[0x1840])))
#define CNTR0_R(d) (d = (readl(&REGS->r[0x0841]) >> 16))
#define CNTR0_W(d) (writel(d << 16, &REGS->r[0x0841]))
#define CNTR0_POLL(d) (d = (readl(&REGS->r[0x1841])))

/* COUNTER1 WORK AND COUNTER1 REGISTERS (32-Bit) (R/W) */
#define CNTR1_WORK_R(d) (d = (readl(&REGS->r[0x0842]) >> 16))
#define CNTR1_WORK_W(d) (writel(d << 16, &REGS->r[0x0842]))
#define CNTR1_WORK_POLL(d) (d = (readl(&REGS->r[0x1842])))
#define CNTR1_R(d) (d = (readl(&REGS->r[0x0843]) >> 16))
#define CNTR1_W(d) (writel(d << 16, &REGS->r[0x0843]))
#define CNTR1_POLL(d) (d = (readl(&REGS->r[0x1843])))

/* TIMER0 WORK AND TIMER0 REGISTERS (32-Bit) (R/W) */
#define TMR0_WORK_R(d) (d = (readl(&REGS->r[0x0844]) >> 16))
#define TMR0_WORK_W(d) (writel(d << 16, &REGS->r[0x0844]))
#define TMR0_WORK_POLL(d) (d = (readl(&REGS->r[0x1844])))
#define TMR0_R(d) (d = (readl(&REGS->r[0x0845]) >> 16))
#define TMR0_W(d) (writel(d << 16, &REGS->r[0x0845]))
#define TMR0_POLL(d) (d = (readl(&REGS->r[0x1845])))

/* TIMER1 WORK AND TIMER1 REGISTERS (32-Bit) (R/W) */
#define TMR1_WORK_R(d) (d = (readl(&REGS->r[0x0846]) >> 16))
#define TMR1_WORK_W(d) (writel(d << 16, &REGS->r[0x0846]))
#define TMR1_WORK_POLL(d) (d = (readl(&REGS->r[0x1846])))
#define TMR1_R(d) (d = (readl(&REGS->r[0x0847]) >> 16))
#define TMR1_W(d) (writel(d << 16, &REGS->r[0x0847]))
#define TMR1_POLL(d) (d = (readl(&REGS->r[0x1847])))

/* OVEN TIMER REGISTERS (32-Bit) (R/W) */
#define OVEN_WORK_R(d) (d = (readl(&REGS->r[0x0848]) >> 16))
#define OVEN_WORK_W(d) (writel(d << 16, &REGS->r[0x0848]))
#define OVEN_TMR_R(d) (d = (readl(&REGS->r[0x0849]) >> 16))
#define OVEN_TMR_W(d) (writel(d << 16, &REGS->r[0x0849]))

/* ----------------- CONTROL AND STATUS REGISTERS ---------------- */
/* TEST REGISTER (32-BIT) (R/W) */
#define TEST_REG_R(d) (d = (readl(&REGS->r[0x100C]) & BYT0))
#define TEST_REG_W(d) (writel(d & BYT0, &REGS->r[0x100C]))

/* DIO CONTROL REGISTER (32-BIT) (R/W) */
#define DIO_CTRL_R(d) (d = (readl(&REGS->r[0x100D]) & BYT1))
#define DIO_CTRL_W(d) (writel(d & BYT1, &REGS->r[0x100D]))

/* ADC FAST PACER CLOCK RATE REGISTERS (32-Bit) (R/W) */
#define AD_FASTCLK_R(d) (d = (readl(&REGS->r[0x100E]) & FMASK))
#define AD_FASTCLK_W(d) (writel(d & FMASK, &REGS->r[0x100E]))

/* DAC0 FAST PACER CLOCK RATE REGISTER (32-Bit) (R/W) */
#define DA0_FASTCLK_R(d) (d = ((readl(&REGS->r[0x100F])) & PMASK) >> 6)
#define DA0_FASTCLK_W(d) (writel(((d << 6) & PMASK), &REGS->r[0x100F]))

/* COUNTER0 CONTROL AND STATUS REGISTER (32-Bit) (R/W) */
#define CNTR0_CTRL_R(d) (d = (readl(&REGS->r[0x1040]) & CNT0))
#define CNTR0_CTRL_W(d) (writel(d & CNT0, &REGS->r[0x1040]))

/* COUNTER1 CONTROL AND STATUS REGISTER (32-Bit) (R/W) */
#define CNTR1_CTRL_R(d) (d = (readl(&REGS->r[0x1042]) & CNT1))
#define CNTR1_CTRL_W(d) (writel(d & CNT1, &REGS->r[0x1042]))

/* TIMER0 CONTROL AND STATUS REGISTER (32-Bit) (R/W) */
#define TMR0_CTRL_R(d) (d = (readl(&REGS->r[0x1044]) & TMR0))
#define TMR0_CTRL_W(d) (writel(d & TMR0, &REGS->r[0x1044]))

/* TIMER1 CONTROL AND STATUS REGISTER (32-Bit) (R/W) */
#define TMR1_CTRL_R(d) (d = (readl(&REGS->r[0x1046]) & TMR1))
#define TMR1_CTRL_W(d) (writel(d & TMR1, &REGS->r[0x1046]))

/* ADC STATUS REGISTER (32-BIT) (R/W) */
#define AD_STATUS_R(d) (d = (readl(&REGS->r[0x1048])) & (LSW))
#define AD_STATUS_W(d) (writel(d & (LSW), &REGS->r[0x1048]))

/* DAC0 STATUS REGISTER (32-BIT) (R/W) */
#define DA0_STATUS_R(d) (d = (readl(&REGS->r[0x1049])) & (D0SMASK))
#define DA0_STATUS_W(d) (writel(d & (D0SMASK), &REGS->r[0x1049]))

/* DAC1 STATUS REGISTER (32-BIT) (R/W) */
#define DA1_STATUS_R(d) (d = (readl(&REGS->r[0x104B])) & (D1SMASK))
#define DA1_STATUS_W(d) (writel(d & (D1SMASK), &REGS->r[0x104B]))

/* ADC CONTROL REGISTER (32-BIT) (R/W) */
#define AD_CTRL_R(d) (d = (readl(&REGS->r[0x104C])) & (LSW))
#define AD_CTRL_W(d) (writel(d & (LSW), &REGS->r[0x104C]))

/* DAC0 CONTROL REGISTER (32-BIT) (R/W) */
#define DA0_CTRL_R(d) (d = (readl(&REGS->r[0x104D]) & DAC0MASK))
#define DA0_CTRL_W(d) (writel(d & (DAC0MASK), &REGS->r[0x104D]))

/* GLOBAL INTERRUPT STATUS REGISTER (32-BIT) (R/W) */
#define INT_STATUS_R(d) (d = (readl(&REGS->r[0x104E]) & INTMASK) )
#define INT_STATUS_W(d) (writel(d & INTMASK, &REGS->r[0x104E]))

/* DAC1 CONTROL REGISTER (32-BIT) (R/W) */
#define DA1_CTRL_R(d) (d = (readl(&REGS->r[0x104F]) & DAC1MASK))
#define DA1_CTRL_W(d) (writel(d & DAC1MASK, &REGS->r[0x104F]))

#endif

/*--------- SELECTED REGISTER BIT DEFINTIONS -------------- */
#define BIT(x)     (0x00000001 << x)

/* ----------- ADC CHANNEL/GAIN CONFIGURATION REGISTER ---------- */
#define AD_CCRAM_D_CIC ( BIT(15) | BIT(14) )
#define AD_CCRAM_D_CJ  ( BIT(13) | BIT(12) | BIT(11) )
#define AD_CCRAM_D_UB  ( BIT(10) )
#define AD_CCRAM_D_GN  ( BIT(9) | BIT(8) )
#define AD_CCRAM_D_MUX ( BIT(7) | BIT(6) | BIT(5) | BIT(4) |  BIT(3) | BIT(2) | BIT(1) | BIT(0) )
/* ----------------- CONTROL AND STATUS REGISTERS ---------------- */
/* TEST REGISTER (32-BIT) (R/W) */
#define TEST_REG_RST23  (BIT(7))
#define TEST_REG_TCTR1  (BIT(6))
#define TEST_REG_TCTR0  (BIT(5))
#define TEST_REG_OVEN   (BIT(4))
#define TEST_REG_NEQ    (BIT(3))
#define TEST_REG_TMDE   (BIT(2))
#define TEST_REG_TSEL_B1B0 (BIT(1) | BIT(0))
#define TEST_REG_TSEL_B1 BIT(1)
#define TEST_REG_TSEL_B0 BIT(0)

/* DIO CONTROL REGISTER (32-BIT) (R/W) */
#define DIO_CTRL_DDC3   (BIT(15))
#define DIO_CTRL_DDC2   (BIT(14))
#define DIO_CTRL_DDC1   (BIT(13))
#define DIO_CTRL_DDC0   (BIT(12))
#define DIO_CTRL_CMDE   (BIT(11))
#define DIO_CTRL_CRUN   (BIT(10))
#define DIO_CTRL_D3SEL  (BIT(9))
#define DIO_CTRL_CONV   (BIT(8))
#define DIO_CTRL_BUSY   (BIT(8))

/* DIO Channel Definitions */
#define DIO_DIO15      (BIT(15))
#define DIO_DIO14      (BIT(14))
#define DIO_DIO13      (BIT(13))
#define DIO_DIO12      (BIT(12))
#define DIO_DIO11      (BIT(11))
#define DIO_DIO10      (BIT(10))
#define DIO_DIO9       (BIT(9))
#define DIO_DIO8       (BIT(8))
#define DIO_DIO7       (BIT(7))
#define DIO_DIO6       (BIT(6))
#define DIO_DIO5       (BIT(5))
#define DIO_DIO4       (BIT(4))
#define DIO_DIO3       (BIT(3))
#define DIO_DIO2       (BIT(2))
#define DIO_DIO1       (BIT(1))
#define DIO_DIO0       (BIT(0))

/* COUNTER0 CONTROL AND STATUS REGISTER (32-Bit) (R/W) */
#define CNTR0_CTRL_ERR  (BIT(2) )
#define CNTR0_CTRL_OVF  (BIT(1) )
#define CNTR0_CTRL_ENA  (BIT(0) )

/* COUNTER1 CONTROL AND STATUS REGISTER (32-Bit) (R/W) */
#define CNTR1_CTRL_ERR  (BIT(6) )
#define CNTR1_CTRL_OVF  (BIT(5) )
#define CNTR1_CTRL_ENA  (BIT(4) )

/* TIMER0 CONTROL AND STATUS REGISTER (32-Bit) (R/W) */
#define TMR0_CTRL_ENA  (BIT(3) )

/* TIMER1 CONTROL AND STATUS REGISTER (32-Bit) (R/W) */
#define TMR1_CTRL_ENA  (BIT(7) )

/* ADC STATUS REGISTER (32-BIT) (R/W) */
#define AD_STATUS_MPRF1  (BIT(15))
#define AD_STATUS_MPRF0  (BIT(14))
#define AD_STATUS_MERR1  (BIT(13))
#define AD_STATUS_MERR0  (BIT(12))
#define AD_STATUS_FFEN   (BIT(11))
#define AD_STATUS_FOVR   (BIT(10))
#define AD_STATUS_FUNDR  (BIT(9))
#define AD_STATUS_CERR   (BIT(8))
#define AD_STATUS_BERR   (BIT(7))
#define AD_STATUS_CCTC   (BIT(6))
#define AD_STATUS_DMATC1 (BIT(5))
#define AD_STATUS_DMATC0 (BIT(4))
#define AD_STATUS_FF     (BIT(3))
#define AD_STATUS_FNE    (BIT(2))
#define AD_STATUS_GATE   (BIT(1))
#define AD_STATUS_CONV   (BIT(0))
#define AD_STATUS_READY  (BIT(0))
#define AD_STATUS_ERROR  (BIT(10)|BIT(9)|BIT(8)|BIT(7))

/* DAC0 STATUS REGISTER (32-BIT) (R/W) */
#define DA0_STATUS_MPRF1  (BIT(15))
#define DA0_STATUS_MPRF0  (BIT(14))
#define DA0_STATUS_MERR1  (BIT(13))
#define DA0_STATUS_MERR0  (BIT(12))
#define DA0_STATUS_FFEN   (BIT(11))
#define DA0_STATUS_FOVR   (BIT(10))
#define DA0_STATUS_DERR   (BIT(9))
#define DA0_STATUS_CERR   (BIT(8))
#define DA0_STATUS_DMATC1 (BIT(5))
#define DA0_STATUS_DMATC0 (BIT(4))
#define DA0_STATUS_FF     (BIT(3))
#define DA0_STATUS_FNE    (BIT(2))
#define DA0_STATUS_GATE   (BIT(1))
#define DA0_STATUS_CONV  (BIT(0))
#define DA0_STATUS_READY (BIT(0))
#define DA0_STATUS_ERROR  (BIT(13)|BIT(12)|BIT(10)|BIT(9)|BIT(8))

/* DAC1 STATUS REGISTER (32-BIT) (R/W) */
#define DA1_STATUS_MPRF1  (BIT(15))
#define DA1_STATUS_MPRF0  (BIT(14))
#define DA1_STATUS_MERR1  (BIT(13))
#define DA1_STATUS_MERR0  (BIT(12))
#define DA1_STATUS_FFEN   (BIT(11))
#define DA1_STATUS_FOVR   (BIT(10))
#define DA1_STATUS_DERR   (BIT(9))
#define DA1_STATUS_CERR   (BIT(8))
#define DA1_STATUS_DMATC1 (BIT(5))