pci550x.h

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/*
 * pci550x.h -- definitions 
 */

#ifndef _PCI550X_H_
#define _PCI550X_H_

/* Board Names - <<< DO NOT CHANGE THE ORDER OF THIS TABLE >>> */
static const char *brd_names[] =
                { "PCI-5500MF  ", "PCI-5501MF  ", "PCI-5501MF-V",
                "PCI-5502MF  ", "PCI-5502MF-V", "PCI-5503HR  ",
                "PCI-5503HR-V", "PCI-5504HR  ", "PCI-5504HR-V" };

/*
 * Channel Configuration RAM
 */
#define ADC_CCRAM_MAX  176
#define ADC_CCRAM_MIN  1
typedef struct adc_ccram {
	unsigned int elements;   /* number of elements */
	unsigned int ccram[ADC_CCRAM_MAX]; 
} adc_ccram;

#ifdef _PCI550X_USE_ADC_RANGE_TABLES
/*
 * ADC Range Tables (indexed by board type)
 */
static struct adc_range_table {
	double bp_res[4];	/* bipolar resolution - Volts/lsb */
	double up_res[4];	/* unipolar resolution - Volts/lsb */
	unsigned char channels; /* number channels */
} art[9] = {
	{ {.00500,.00500,.00500,.00500},/* PCI-5500MF */
	{.00250,.00250,.00250,.00250}, 8 },

	{ {.00500,.00250,.001250,.0006250},/*PCI-5501MF*/
	{.00250,.00125,.000625,.0003125}, 16 },

	{ {.00500,.00250,.001250,.0006250},/*PCI-5501MF-V*/
	{.00250,.00125,.000625,.0003125}, 16 },

	{ {.00500,.000500,.0000500,.00000500},/*PCI-5502MF*/
	{.00250,.000250,.0000250,.00000250 }, 16 },

	{ {.00500,.000500,.0000500,.00000500},/*PCI-5502MF-V*/
	{.00250,.000250,.0000250,.00000250 }, 16 },

	{ {.000310140,.0001550700,.0000775350,.0000387680},/*PCI-5503MF*/
	{.000155070,.0000775350,.0000387680,.0000193840 }, 16 },

	{ {.000310140,.0000310140,.00000310140,.000000310140},/*PCI-5504MF*/
	{.000155070,.0000155070,.00000155070,.000000155070}, 16 },

	{ {.000310140,.0000310140,.00000310140,.000000310140},/*PCI-5504MF-V*/
	{.000155070,.0000155070,.00000155070,.000000155070}, 16 },
};
#endif

#ifdef _PCI550X_USE_DAC_RANGE_TABLES
/*
 * DAC Range Table (all boards)
 */
static struct dac_range_table {
	short bp_min;	/* bipolar DAC min raw count */
	short bp_max;	/* bipolar DAC max raw count */
	double bp_res;	/* bipolar resolution - Volts/lsb */
	unsigned short up_min;	/* unipolar DAC min raw count */
	unsigned short up_max;	/* unipolar DAC max raw count */
	double up_res;	/* unipolar resolution - Volts/lsb */
} drt = {-32723, 32722, .000305600, 0, 65445, .0001528 };
#endif

#define PCI550X_TRUE 1
#define PCI550X_FALSE 0

#define PCI550X_NOMINAL_ADC_RATE 10 /* nominal ADC sample rate (usecs) */
#define PCI550X_FAST_ADC_RATE 5	    /* fast ADC sample rate (usecs) */

#define PCI550X_MIN_ADC_RATE 5	/* min ADC rate per sample in usecs */

#define PCI550X_NOMINAL_DAC_RATE 10 /* nominal DAC sample rate (usecs) */
#define PCI550X_FAST_DAC_RATE 5	    /* fast DAC sample rate (usecs) */

#define PCI550X_MIN_DAC_RATE 5	/* min DAC rate per sample in usecs */

#define PCI550X_DAC0 0	/* select DAC0 channel for write DMA */
#define PCI550X_DAC1 1	/* select DAC1 channel for write DMA */
#define PCI550X_DAC_FIFO 64	/* number DAC FIFO entries */

#ifdef __KERNEL__

#include <linux/pci.h>
#include <linux/fs.h>
#include <asm/io.h>
#include <asm/semaphore.h>

#define PCI_VENDOR_ID_ADAC 0x1633
#define PCI_SUBVENDOR_ID_ADAC 0x1633
#define PCI_SUBSYSTEM_ID_A 0x0000
#define PCI_SUBSYSTEM_ID_B 0x0201
#define PCI_DEVICE_ID_5500MF 0x157C
#define PCI_DEVICE_ID_5501MF 0x157D
#define PCI_DEVICE_ID_5501MFV 0x157D
#define PCI_DEVICE_ID_5502MF 0x157E
#define PCI_DEVICE_ID_5502MFV 0x157E
#define PCI_DEVICE_ID_5503HR 0x157F
#define PCI_DEVICE_ID_5503HRV 0x157F
#define PCI_DEVICE_ID_5504HR 0x1580
#define PCI_DEVICE_ID_5504HRV 0x1580

#ifndef PCI550X_MAJOR
#define PCI550X_MAJOR 0
#endif

#ifndef PCI550X_USE_PROC
#define PCI550X_USE_PROC 1
#endif

#define PCI550X_ENABLED 1
#define PCI550X_DISABLED 0

#define PCI550X_SET 1
#define PCI550X_RESET 0

#define PCI550X_DIO_OUTPUT 1
#define PCI550X_DIO_INPUT 0

#define PCI550X_PFX "pci550x: "

#define PCI550X_MAX_DMA_BYTES 65536
#define PCI550X_DMA_PAGES ((PCI550X_MAX_DMA_BYTES+PAGE_SIZE-1)/PAGE_SIZE)

#define PCI550X_CAL_PAGES 12 /* number of calibration pages */

/* Board Types - <<< DO NOT CHANGE THE ORDER OF THIS TABLE >>> */
enum board_types {
	pci5500mf = 0, pci5501mf, pci5501mfv, pci5502mf, pci5502mfv,
	pci5503hr, pci5503hrv, pci5504hr, pci5504hrv,
};

/*
 * ADC statistics block
 */
typedef struct pci550x_adc_stats {
	unsigned int merr0;
	unsigned int merr1;
	unsigned int fovr;
	unsigned int fundr;
	unsigned int cerr;
	unsigned int berr;
} pci550x_adc_stats;

/*
 * DAC statistics block
 */
typedef struct pci550x_dac0_stats {
	unsigned int merr0;
	unsigned int merr1;
	unsigned int fovr;
	unsigned int derr;
	unsigned int cerr;
} pci550x_dac_stats;

/*
 * driver device instance block 
 */
typedef struct pci550x_dib_s {
	const char* brd_name;
	unsigned char brd_type, brd_status, opened, adc_opened, dac_opened;
	unsigned int minor, irq;
	u_int8_t brd_rev;
	struct pci_dev* pdev;
	spinlock_t reg_lock;
	spinlock_t open_lock;
	spinlock_t adc_lock;
	spinlock_t dac_lock;
	struct semaphore sem;
	unsigned long addr;	/* memory address - unmapped */
	size_t len;		/* size in bytes */
	void *membase;		/* memory address - mapped */
	adc_ccram ccram;	/* ccram shadow */
	u_int32_t int_status;	/* latest interrupt status */
	u_int32_t adc_status;	/* latest adc status */
	u_int32_t adc_ctrl;	/* latest adc control */
	u_int32_t dac0_status;	/* latest dac0 status */
	u_int32_t dac0_ctrl;	/* latest dac0 control */
	u_int32_t dac1_status;	/* latest dac1 status */
	u_int32_t dac1_ctrl;	/* latest dac1 control */
	int dac_select;		/* current DMA DAC channel */

	u_int32_t *adc_dma_buf0;
	dma_addr_t adc_dma_handle0;
	u_int32_t *adc_dma_buf1;
	dma_addr_t adc_dma_handle1;
	unsigned long adc_dma_page_order;
	unsigned long adc_timeout;
	int adc_dma_bytes;
	u_int32_t adc_dma_mcr;

	u_int32_t *dac0_dma_buf0;
	dma_addr_t dac0_dma_handle0;
	u_int32_t *dac0_dma_buf1;
	dma_addr_t dac0_dma_handle1;
	unsigned long dac0_dma_page_order;
	unsigned long dac0_timeout;
	int dac0_dma_bytes;
	u_int32_t dac0_dma_mcr;

	u_int32_t *dac1_dma_buf0;
	dma_addr_t dac1_dma_handle0;
	u_int32_t *dac1_dma_buf1;
	dma_addr_t dac1_dma_handle1;
	unsigned long dac1_dma_page_order;
	unsigned long dac1_timeout;
	int dac1_dma_bytes;
	u_int32_t dac1_dma_mcr;

	wait_queue_head_t adc_wq;
	wait_queue_head_t dac0_wq;
	wait_queue_head_t dac1_wq;

	struct proc_dir_entry *proc;
	pci550x_adc_stats adc_stats;
	pci550x_dac_stats dac0_stats;
	pci550x_dac_stats dac1_stats;

} pci550x_dib;

/* function prototypes */
static int pci550x_open(struct inode*, struct file*);
static int pci550x_release(struct inode*, struct file*);
static int pci550x_ioctl(struct inode*, struct file*,
             unsigned int, unsigned long);
static ssize_t pci550x_read(struct file*, char *, size_t, loff_t *);
static ssize_t pci550x_readv(struct file*, const struct iovec *,
	unsigned long, loff_t *);
static ssize_t pci550x_write(struct file*, const char *, size_t, loff_t *);
static ssize_t pci550x_writev(struct file*, const struct iovec *,
	unsigned long, loff_t *);
static void pci550x_interrupt(int, void*, struct pt_regs*);

static int pci550x_adc_reset(pci550x_dib*);
static int pci550x_dac0_reset(pci550x_dib*);
static int pci550x_dac1_reset(pci550x_dib*);
static void pci550x_free_adc_buffs(pci550x_dib*);
static void pci550x_free_dac0_buffs(pci550x_dib*);
static void pci550x_free_dac1_buffs(pci550x_dib*);
static int pci550x_read_procmem(char *, char **, off_t, int, int *, void *);
static int pci550x_calibrate(pci550x_dib*);

/*
 * HW Register MAP (64KB)
 */
#define SZ_WORDS (1024 * 16)
volatile typedef struct pci550x_hwregs {
	u_int32_t  r[SZ_WORDS];
} pci550x_hwregs; 

/*
 * Clock Rates
 */
#define NOMINAL_CLOCK 1000000   /* 1MHZ Nominal Clock Rate */
#define FAST_CLOCK    4000000   /* 4MHZ Fast Clock Rate */

/*
 * HW Register MAP Definitions
 */
#define LSW        0x0000ffff   /* lsw mask */
#define MSW        0xffff0000   /* msw mask */
#define BYT0       0x000000ff   /* byte 0 mask */
#define BYT1       0x0000ff00   /* byte 1 mask */
#define BYT2       0x00ff0000   /* byte 2 mask */
#define BYT3       0xff000000   /* byte 3 mask */
#define PMASK      0x00000fc0   /* clock mask */
#define FMASK      0x0000003f   /* clock mask */
#define D0SMASK    0x0000ff3f   /* DA0 status mask */
#define D1SMASK    0x0000ff3d   /* DA1 status mask */
#define DAC0MASK   0x0000eb7d   /* DA0 control mask */
#define DAC1MASK   0x0000eb00   /* DA1 control mask */
#define TMR0       0x00000008   /* timer 0 control mask */
#define TMR1       0x00000080   /* timer 1 control mask */
#define CNT0       0x00000007   /* counter 0 control mask */
#define CNT1       0x00000070   /* counter 1 control mask */
#define INTMASK    0x000000bb   /* global interrrupt status mask */

/* --------------------- DATA FIFO REGISTERS --------------*/
#define AD_FIFO_R (readl(&REGS->r[0x0100]))
#define DA0_FIFO_W(d) (writel(d , &REGS->r[0x0104]))
#define DA1_FIFO_W(d) (writel(d, &REGS->r[0x010C]))
#define DIO_REG_R(d) (d = ((readl(&REGS->r[0x0902])) & LSW))
#define DIO_REG_W(d) (writel(d & LSW, &REGS->r[0x0902]))

/* --------------- CALIBRATION MEMORY ARRAY --------------*/
#define CAL_MEMORY_ARRAY_R(d,o) (d = readl(&REGS->r[0x0400+o]))
#define CAL_MEMORY_ARRAY_W(d,o) (writel(d,&REGS->r[0x0400+o]))
#define CAL_MEM_ADC_OFFSETS_R(d,o) (d = readl(&REGS->r[0x0700+o]))
#define CAL_MEM_ADC_OFFSETS_W(d,o) (writel(d,&REGS->r[0x0700+o]))

/* ----------- ADC CHANNEL/GAIN CONFIGURATION REGISTER ---------- */
#define AD_CCRAM_D_R(d,o) (d = (readl(&REGS->r[0x0850+o]) >> 16))
#define AD_CCRAM_D_W(d,o) (writel(d << 16, &REGS->r[0x0850+o]))
#define AD_CCRAM_I_W      (writel(0, &REGS->r[0x0900]))

/* ------ MISCELLANEOUS ADC CYCLE CONTROL AND POINTER REGISTERS  -------- */
#define AD_SADDR_WORK_R(d) (d = (readl(&REGS->r[0x0800]) >> 16))
#define AD_SADDR_WORK_W(d) (writel(d << 16, &REGS->r[0x0800]))
#define AD_SADDR_R(d) (d = (readl(&REGS->r[0x0801]) >> 16))
#define AD_SADDR_W(d) (writel(d << 16, &REGS->r[0x0801]))

/* ------ SPECIAL PURPOSE AND ADDITIONAL MRA REGISTERS GO HERE --------- */
#define THESE_ARE_TBD 0

/* ------------------ PARALLEL DIGITAL I/O REGISTERS --------------- */
#define DIO_0_R(d) (d = (readl(&REGS->r[0x020D]) & BYT0))
#define DIO_0_W(d) (writel(d & BYT0, &REGS->r[0x020D]))
#define DIO_1_R(d) (d = ((readl(&REGS->r[0x020E]) & BYT1)>>8))
#define DIO_1_W(d) (writel((d<<8) & BYT1, &REGS->r[0x020E]))
#define DIO_16_R(d) (d = (readl(&REGS->r[0x020F]) & LSW))
#define DIO_16_W(d) (writel(d & LSW, &REGS->r[0x020F]))

/* EVENT DEPENDENT PACER AND PACER WORK REGISTERS (32-Bit) (R/W) */
#define AD_PACERL_WORK_R(d) (d = (readl(&REGS->r[0x0810]) >> 16))
#define AD_PACERL_WORK_W(d) (writel(d << 16, &REGS->r[0x0810]))
#define AD_PACERL_R(d) (d = (readl(&REGS->r[0x0811]) >> 16))
#define AD_PACERL_W(d) (writel(d << 16, &REGS->r[0x0811]))
#define AD_PACERH_WORK_R(d) (d = (readl(&REGS->r[0x0812]) >> 16))
#define AD_PACERH_WORK_W(d) (writel(d << 16, &REGS->r[0x0812]))
#define AD_PACERH_R(d) (d = (readl(&REGS->r[0x0813]) >> 16))
#define AD_PACERH_W(d) (writel(d << 16, &REGS->r[0x0813]))