📄 startlpc.lst
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A51 MACRO ASSEMBLER STARTLPC 11/29/2007 15:41:52 PAGE 1
MACRO ASSEMBLER A51 V7.09
OBJECT MODULE PLACED IN STARTLPC.OBJ
ASSEMBLER INVOKED BY: D:\Program Files\Keil\C51\BIN\A51.EXE STARTLPC.A51 SET(SMALL) DEBUG EP
LOC OBJ LINE SOURCE
1 ;------------------------------------------------------------------------------
2 ; This file is part of the C51 Compiler package
3 ; Startup Code for the Philips LPC series
4 ; Copyright (c) 1988-2001 Keil Elektronik GmbH and Keil Software, Inc.
5 ;------------------------------------------------------------------------------
6 ; STARTLPC.A51: This code is executed after processor reset.
7 ; You may add this file to a uVision2 project.
8 ;
9 ; To translate this file use Ax51 with the following invocation:
10 ;
11 ; Ax51 STARTLPC.A51
12 ;
13 ; To link the modified STARTLPC.OBJ file to your application use the following
14 ; Lx51 invocation:
15 ;
16 ; Lx51 <your object file list>, STARTLPC.OBJ <controls>
17 ;
18 ;------------------------------------------------------------------------------
19 ;
20 ; User-defined Power-On Initialization of Memory
21 ;
22 ; With the following EQU statements the initialization of memory
23 ; at processor reset can be defined:
24 ;
25 ; ; the absolute start-address of IDATA memory is always 0
0080 26 IDATALEN EQU 80H ; the length of IDATA memory in bytes.
27 ;
28 ;
29 ; Notes: The IDATA space overlaps physically the DATA and BIT areas of the
30 ; 8051 CPU. At minimum the memory space occupied from the C51
31 ; run-time routines must be set to zero.
32 ;------------------------------------------------------------------------------
33 ;
34 ; Reentrant Stack Initilization
35 ;
36 ; The following EQU statements define the stack pointer for reentrant
37 ; functions and initialized it:
38 ;
39 ; Stack Space for reentrant functions in the SMALL model.
0000 40 IBPSTACK EQU 0 ; set to 1 if small reentrant is used.
0080 41 IBPSTACKTOP EQU 07FH+1 ; set top of stack to highest location+1.
42 ;
43 ;------------------------------------------------------------------------------
44 ;
45 ; Setup LPC Configuration Register (UCFG1, UCFG2)
46 ;
47 ; Oscillator Configuration (UCFG1.0 .. UCFG1.2)
48 ; FOSC Val Description
49 ; ---- --- -----------
0007 50 FOSC EQU 7 ; 0 = high frequency crystal or resonator (4MHz .. 20MHz)
51 ; ; 1 = medium frequency crystal or resonator (100kHz .. 4MHz)
52 ; ; 2 = low frequency crystal (20kHz .. 100kHz)
53 ; ; 3 = internal RC oscillator (6MHz +/- 25%)
54 ; ; 7 = (default on unprogrammed part) external clock input on X1
55 ;
56 ; Clock Rate Select (UCFG1.3)
57 ; CLKR Val Description
58 ; ---- --- -----------
A51 MACRO ASSEMBLER STARTLPC 11/29/2007 15:41:52 PAGE 2
0001 59 CLKR EQU 1 ; 0 = CPU clock devided by 2 (results in 12 CPU clocks like on 8051)
60 ; ; 1 = (default on unprogrammed part) fast CPU clock (6 CPU clocks)
61 ;
62 ; Brownout Voltage Select (UCFG1.4)
63 ; BOV Val Description
64 ; ---- --- -----------
0001 65 BOV EQU 1 ; 0 = Brownout detect voltage = 3.8V
66 ; ; 1 = Brownout detect voltage = 2.5V
67 ;
68 ; Port reset state (UCFG1.5)
69 ; PRHI Val Description
70 ; ---- --- -----------
0001 71 PRHI EQU 1 ; 0 = Ports reset to a low state
72 ; ; 1 = (default on unprogrammed part) Ports reset to a high state
73 ;
74 ; Reset PIN disable (UCFG1.6)
75 ; RPD Val Description
76 ; --- --- -----------
0001 77 RPD EQU 1 ; 0 = P1.5 will act as reset pin (low active)
78 ; ; 1 = (default on unprogrammed part) P1.5 can be used as input PIN
79 ;
80 ; Watchdog timer enable (UCFG1.7)
81 ; WDTE Val Description
82 ; ---- --- -----------
0001 83 WDTE EQU 1 ; 0 = watchdog disabled (watch can still be a timer to generate interrupts)
84 ; ; 1 = (default on unprogrammed part) watchdog enabled
85 ;
86 ;
87 ; EPROM Security (UCFG2.6 .. UCFG2.7)
88 ; SB Val Description
89 ; -- --- -----------
0003 90 SB EQU 3 ; 0 = EPROM verification and programming disabled
91 ; ; 2 = further EPROM programming is disabled
92 ; ; 3 = no security features enabled; EPROM is programmable and verifiable.
93 ;
94 ;------------------------------------------------------------------------------
95
96 NAME ?C_STARTUP
97
00FF 98 _UCFG1 EQU FOSC OR (CLKR SHL 3) OR (BOV SHL 4) OR (PRHI SHL 5) OR (RPD SHL 6) OR (WDTE SHL
7)
00FF 99 _UCFG2 EQU (SB SHL 6) OR 0x3F
100
---- 101 CSEG AT 0FD00H
FD00 FF 102 DB _UCFG1 ; place UCFG Bytes in ROM
FD01 FF 103 DB _UCFG2
104
105
106 ?C_C51STARTUP SEGMENT CODE
107 ?STACK SEGMENT IDATA
108
---- 109 RSEG ?STACK
0000 110 DS 1
111
112 EXTRN CODE (?C_START)
113 PUBLIC ?C_STARTUP
114
---- 115 CSEG AT 0
0000 020000 F 116 ?C_STARTUP: JMP STARTUP1
117
---- 118 RSEG ?C_C51STARTUP
119
0000 120 STARTUP1:
121
122 IF IDATALEN <> 0
0000 787F 123 MOV R0,#IDATALEN - 1
A51 MACRO ASSEMBLER STARTLPC 11/29/2007 15:41:52 PAGE 3
0002 E4 124 CLR A
0003 F6 125 IDATALOOP: MOV @R0,A
0004 D8FD 126 DJNZ R0,IDATALOOP
127 ENDIF
128
129
130 IF IBPSTACK <> 0
EXTRN DATA (?C_IBP)
MOV ?C_IBP,#LOW IBPSTACKTOP
ENDIF
135
0006 758100 F 136 MOV SP,#?STACK-1
0009 020000 F 137 JMP ?C_START
138
139 END
A51 MACRO ASSEMBLER STARTLPC 11/29/2007 15:41:52 PAGE 4
SYMBOL TABLE LISTING
------ ----- -------
N A M E T Y P E V A L U E ATTRIBUTES
?C_C51STARTUP. . . C SEG 000CH REL=UNIT
?C_START . . . . . C ADDR ----- EXT
?C_STARTUP . . . . C ADDR 0000H A
?STACK . . . . . . I SEG 0001H REL=UNIT
BOV. . . . . . . . N NUMB 0001H A
CLKR . . . . . . . N NUMB 0001H A
FOSC . . . . . . . N NUMB 0007H A
IBPSTACK . . . . . N NUMB 0000H A
IBPSTACKTOP. . . . N NUMB 0080H A
IDATALEN . . . . . N NUMB 0080H A
IDATALOOP. . . . . C ADDR 0003H R SEG=?C_C51STARTUP
PRHI . . . . . . . N NUMB 0001H A
RPD. . . . . . . . N NUMB 0001H A
SB . . . . . . . . N NUMB 0003H A
SP . . . . . . . . D ADDR 0081H A
STARTUP1 . . . . . C ADDR 0000H R SEG=?C_C51STARTUP
WDTE . . . . . . . N NUMB 0001H A
_UCFG1 . . . . . . N NUMB 00FFH A
_UCFG2 . . . . . . N NUMB 00FFH A
REGISTER BANK(S) USED: 0
ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)
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