📄 ioat91sam7a3.h
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// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
// *****************************************************************************
typedef struct _AT91S_RTTC {
AT91_REG RTTC_RTMR; // Real-time Mode Register
AT91_REG RTTC_RTAR; // Real-time Alarm Register
AT91_REG RTTC_RTVR; // Real-time Value Register
AT91_REG RTTC_RTSR; // Real-time Status Register
} AT91S_RTTC, *AT91PS_RTTC;
// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
// *****************************************************************************
typedef struct _AT91S_PITC {
AT91_REG PITC_PIMR; // Period Interval Mode Register
AT91_REG PITC_PISR; // Period Interval Status Register
AT91_REG PITC_PIVR; // Period Interval Value Register
AT91_REG PITC_PIIR; // Period Interval Image Register
} AT91S_PITC, *AT91PS_PITC;
// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
// *****************************************************************************
typedef struct _AT91S_WDTC {
AT91_REG WDTC_WDCR; // Watchdog Control Register
AT91_REG WDTC_WDMR; // Watchdog Mode Register
AT91_REG WDTC_WDSR; // Watchdog Status Register
} AT91S_WDTC, *AT91PS_WDTC;
// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Memory Controller Interface
// *****************************************************************************
typedef struct _AT91S_MC {
AT91_REG MC_RCR; // MC Remap Control Register
AT91_REG MC_ASR; // MC Abort Status Register
AT91_REG MC_AASR; // MC Abort Address Status Register
AT91_REG Reserved0[1]; //
AT91_REG MC_PUIA[16]; // MC Protection Unit Area
AT91_REG MC_PUP; // MC Protection Unit Peripherals
AT91_REG MC_PUER; // MC Protection Unit Enable Register
AT91_REG Reserved1[2]; //
AT91_REG MC_FMR; // MC Flash Mode Register
AT91_REG MC_FCR; // MC Flash Command Register
AT91_REG MC_FSR; // MC Flash Status Register
} AT91S_MC, *AT91PS_MC;
// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
#define AT91C_MC_MPU ((unsigned int) 0x1 << 2) // (MC) Memory protection Unit Abort Status
#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area --------
#define AT91C_MC_PROT ((unsigned int) 0x3 << 0) // (MC) Protection
#define AT91C_MC_PROT_PNAUNA ((unsigned int) 0x0) // (MC) Privilege: No Access, User: No Access
#define AT91C_MC_PROT_PRWUNA ((unsigned int) 0x1) // (MC) Privilege: Read/Write, User: No Access
#define AT91C_MC_PROT_PRWURO ((unsigned int) 0x2) // (MC) Privilege: Read/Write, User: Read Only
#define AT91C_MC_PROT_PRWURW ((unsigned int) 0x3) // (MC) Privilege: Read/Write, User: Read/Write
#define AT91C_MC_SIZE ((unsigned int) 0xF << 4) // (MC) Internal Area Size
#define AT91C_MC_SIZE_1KB ((unsigned int) 0x0 << 4) // (MC) Area size 1KByte
#define AT91C_MC_SIZE_2KB ((unsigned int) 0x1 << 4) // (MC) Area size 2KByte
#define AT91C_MC_SIZE_4KB ((unsigned int) 0x2 << 4) // (MC) Area size 4KByte
#define AT91C_MC_SIZE_8KB ((unsigned int) 0x3 << 4) // (MC) Area size 8KByte
#define AT91C_MC_SIZE_16KB ((unsigned int) 0x4 << 4) // (MC) Area size 16KByte
#define AT91C_MC_SIZE_32KB ((unsigned int) 0x5 << 4) // (MC) Area size 32KByte
#define AT91C_MC_SIZE_64KB ((unsigned int) 0x6 << 4) // (MC) Area size 64KByte
#define AT91C_MC_SIZE_128KB ((unsigned int) 0x7 << 4) // (MC) Area size 128KByte
#define AT91C_MC_SIZE_256KB ((unsigned int) 0x8 << 4) // (MC) Area size 256KByte
#define AT91C_MC_SIZE_512KB ((unsigned int) 0x9 << 4) // (MC) Area size 512KByte
#define AT91C_MC_SIZE_1MB ((unsigned int) 0xA << 4) // (MC) Area size 1MByte
#define AT91C_MC_SIZE_2MB ((unsigned int) 0xB << 4) // (MC) Area size 2MByte
#define AT91C_MC_SIZE_4MB ((unsigned int) 0xC << 4) // (MC) Area size 4MByte
#define AT91C_MC_SIZE_8MB ((unsigned int) 0xD << 4) // (MC) Area size 8MByte
#define AT91C_MC_SIZE_16MB ((unsigned int) 0xE << 4) // (MC) Area size 16MByte
#define AT91C_MC_SIZE_64MB ((unsigned int) 0xF << 4) // (MC) Area size 64MByte
#define AT91C_MC_BA ((unsigned int) 0x3FFFF << 10) // (MC) Internal Area Base Address
// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral --------
// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area --------
#define AT91C_MC_PUEB ((unsigned int) 0x1 << 0) // (MC) Protection Unit enable Bit
// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
#define AT91C_MC_EOP ((unsigned int) 0x1 << 0) // (MC) End Of Programming Flag
#define AT91C_MC_EOL ((unsigned int) 0x1 << 1) // (MC) End Of Lock/Unlock Flag
#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error Flag
#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error Flag
#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
// *****************************************************************************
typedef struct _AT91S_CAN_MB {
AT91_REG CAN_MB_MMR; // MailBox Mode Register
AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
AT91_REG CAN_MB_MID; // MailBox ID Register
AT91_REG CAN_MB_MFID; // MailBox Family ID Register
AT91_REG CAN_MB_MSR; // MailBox Status Register
AT91_REG CAN_MB_MDL; // MailBox Data Low Register
AT91_REG CAN_MB_MDH; // MailBox Data High Register
AT91_REG CAN_MB_MCR; // MailBox Control Register
} AT91S_CAN_MB, *AT91PS_CAN_MB;
// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark
#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB)
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