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<h1>Two-wire Interface Peripheral</h1>
<null><a name="TWI"></a><b>TWI</b> <i><font size="-1">(<a href="AT91SAM7A3_h.html#AT91S_TWI">AT91S_TWI</a>)</font></i><b> 0xFFFB8000 </b><i><font size="-1">(<a href="AT91SAM7A3_h.html#AT91C_BASE_TWI">AT91C_BASE_TWI</a>)</font></i>
<table border=1 cellpadding=3 cellspacing=0><null><th bgcolor="#FFFFCC"><font size="-1">Periph ID <a href="AT91SAM7A3_AIC.html#AIC">AIC</a></font></th><th bgcolor="#FFFFCC"><font size="-1">Symbol</font></th><th bgcolor="#FFFFCC"><font size="-1">Description</font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b>10</b> </font></td><td><font size="-1"><i><font size="-1">(<a href="AT91SAM7A3_h.html#AT91C_ID_TWI">AT91C_ID_TWI</a>)</font></i></font></td><td><font size="-1">Two-Wire Interface</font></td></tr>
</null></table><br><table border=1 cellpadding=3 cellspacing=0><null><th bgcolor="#FFFFCC"><font size="-1"><b>Signal</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Symbol</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>PIO controller</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b>
</font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b>TWCK</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA1_TWCK ">AT91C_PA1_TWCK </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a> Periph: A Bit: 1</font></td><td><font size="-1">TWI Two-wire Serial Clock</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>TWD</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA0_TWD ">AT91C_PA0_TWD </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a> Periph: A Bit: 0</font></td><td><font size="-1">TWI Two-wire Serial Data</font></td></tr>
</null></table><br><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Function</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7A3_h.html#AT91F_TWI_CfgPMC">AT91F_TWI_CfgPMC</a></b></font></td><td><font size="-1">Enable Peripheral clock in PMC for TWI</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7A3_h.html#AT91F_TWI_CfgPIO">AT91F_TWI_CfgPIO</a></b></font></td><td><font size="-1">Configure PIO controllers to drive TWI signals</font></td></tr>
</null></table><br><br></null><a name="TWI"></a><h2>TWI Software API <i><font size="-1">(<a href="AT91SAM7A3_h.html#AT91S_TWI">AT91S_TWI</a>)</font></i></h2>
<a name="TWI"></a><null><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Offset</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Field</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x0</b></font></td><td><font size="-1"><a href="AT91SAM7A3_TWI.html#TWI_CR">TWI_CR</a></font></td><td><font size="-1">Control Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x4</b></font></td><td><font size="-1"><a href="AT91SAM7A3_TWI.html#TWI_MMR">TWI_MMR</a></font></td><td><font size="-1">Master Mode Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0xC</b></font></td><td><font size="-1"><a href="AT91SAM7A3_TWI.html#TWI_IADR">TWI_IADR</a></font></td><td><font size="-1">Internal Address Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x10</b></font></td><td><font size="-1"><a href="AT91SAM7A3_TWI.html#TWI_CWGR">TWI_CWGR</a></font></td><td><font size="-1">Clock Waveform Generator Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x20</b></font></td><td><font size="-1"><a href="AT91SAM7A3_TWI.html#TWI_SR">TWI_SR</a></font></td><td><font size="-1">Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x24</b></font></td><td><font size="-1"><a href="AT91SAM7A3_TWI.html#TWI_IER">TWI_IER</a></font></td><td><font size="-1">Interrupt Enable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x28</b></font></td><td><font size="-1"><a href="AT91SAM7A3_TWI.html#TWI_IDR">TWI_IDR</a></font></td><td><font size="-1">Interrupt Disable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x2C</b></font></td><td><font size="-1"><a href="AT91SAM7A3_TWI.html#TWI_IMR">TWI_IMR</a></font></td><td><font size="-1">Interrupt Mask Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x30</b></font></td><td><font size="-1"><a href="AT91SAM7A3_TWI.html#TWI_RHR">TWI_RHR</a></font></td><td><font size="-1">Receive Holding Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x34</b></font></td><td><font size="-1"><a href="AT91SAM7A3_TWI.html#TWI_THR">TWI_THR</a></font></td><td><font size="-1">Transmit Holding Register</font></td></tr>
</null></table><br><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Function</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7A3_h.html#AT91F_TWI_Configure">AT91F_TWI_Configure</a></b></font></td><td><font size="-1">Configure TWI in master mode</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7A3_h.html#AT91F_TWI_GetInterruptMaskStatus">AT91F_TWI_GetInterruptMaskStatus</a></b></font></td><td><font size="-1">Return TWI Interrupt Mask Status</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7A3_h.html#AT91F_TWI_EnableIt">AT91F_TWI_EnableIt</a></b></font></td><td><font size="-1">Enable TWI IT</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7A3_h.html#AT91F_TWI_DisableIt">AT91F_TWI_DisableIt</a></b></font></td><td><font size="-1">Disable TWI IT</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7A3_h.html#AT91F_TWI_IsInterruptMasked">AT91F_TWI_IsInterruptMasked</a></b></font></td><td><font size="-1">Test if TWI Interrupt is Masked </font></td></tr>
</null></table></null><h2>TWI Register Description</h2>
<null><a name="TWI_CR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91SAM7A3_h.html#AT91_REG">AT91_REG</a></i> TWI_CR <i>Control Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91SAM7A3_h.html#AT91C_TWI_CR">AT91C_TWI_CR</a></i> 0xFFFB8000</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="TWI_START"></a><b>TWI_START</b><font size="-2"><br><a href="AT91SAM7A3_h.html#AT91C_TWI_START">AT91C_TWI_START</a></font></td><td><b>Send a START Condition</b><br>0: No effect.<br>1: A frame beginning with a START bit is transmitted according to the features defined in the mode register.<br>This action is necessary when the TWI peripheral wants to read data from a slave. When configured in master mode with a write operation, a frame is sent with the mode register as soon as the user writes a character in the holding register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="TWI_STOP"></a><b>TWI_STOP</b><font size="-2"><br><a href="AT91SAM7A3_h.html#AT91C_TWI_STOP">AT91C_TWI_STOP</a></font></td><td><b>Send a STOP Condition</b><br>0: No effect.<br>1: STOP Condition is sent just after completing the current byte transmission in master read or write mode.<br>In single data byte master read or write, the START and STOP must both be set.<br>In multiple data bytes master read or write, the STOP must be set before ACK/NACK bit transmission.<br>In master read mode, if a NACK bit is received, the STOP is automatically performed.<br>In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="TWI_MSEN"></a><b>TWI_MSEN</b><font size="-2"><br><a href="AT91SAM7A3_h.html#AT91C_TWI_MSEN">AT91C_TWI_MSEN</a></font></td><td><b>TWI Master Transfer Enabled</b><br>0: No effect.<br>1: If MSDIS = 0, the master data transfer is enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="TWI_MSDIS"></a><b>TWI_MSDIS</b><font size="-2"><br><a href="AT91SAM7A3_h.html#AT91C_TWI_MSDIS">AT91C_TWI_MSDIS</a></font></td><td><b>TWI Master Transfer Disabled</b><br>0: No effect.<br>1: The master data transfer is disabled, all pending data is transmitted. The shifter and holding character (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="TWI_SWRST"></a><b>TWI_SWRST</b><font size="-2"><br><a href="AT91SAM7A3_h.html#AT91C_TWI_SWRST">AT91C_TWI_SWRST</a></font></td><td><b>Software Reset</b><br>0: No effect.<br>1: Equivalent to a system reset.</td></tr>
</null></table>
<a name="TWI_MMR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91SAM7A3_h.html#AT91_REG">AT91_REG</a></i> TWI_MMR <i>Master Mode Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91SAM7A3_h.html#AT91C_TWI_MMR">AT91C_TWI_MMR</a></i> 0xFFFB8004</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..8</td><td align="CENTER"><a name="TWI_IADRSZ"></a><b>TWI_IADRSZ</b><font size="-2"><br><a href="AT91SAM7A3_h.html#AT91C_TWI_IADRSZ">AT91C_TWI_IADRSZ</a></font></td><td><b>Internal Device Address Size</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="TWI_IADRSZ_NO"></a><b>TWI_IADRSZ_NO</b><font size="-1"><br><a href="AT91SAM7A3_h.html#AT91C_TWI_IADRSZ_NO">AT91C_TWI_IADRSZ_NO</a></font></td><td><br>No internal device address</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="TWI_IADRSZ_1_BYTE"></a><b>TWI_IADRSZ_1_BYTE</b><font size="-1"><br><a href="AT91SAM7A3_h.html#AT91C_TWI_IADRSZ_1_BYTE">AT91C_TWI_IADRSZ_1_BYTE</a></font></td><td><br>One-byte internal device address</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="TWI_IADRSZ_2_BYTE"></a><b>TWI_IADRSZ_2_BYTE</b><font size="-1"><br><a href="AT91SAM7A3_h.html#AT91C_TWI_IADRSZ_2_BYTE">AT91C_TWI_IADRSZ_2_BYTE</a></font></td><td><br>Two-byte internal device address</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="TWI_IADRSZ_3_BYTE"></a><b>TWI_IADRSZ_3_BYTE</b><font size="-1"><br><a href="AT91SAM7A3_h.html#AT91C_TWI_IADRSZ_3_BYTE">AT91C_TWI_IADRSZ_3_BYTE</a></font></td><td><br>Three-byte internal device address</td></tr>
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