edma_config.asm

在DM642硬件平台上

* OPT    - options parameter
* SRC    - source address parameter
* CNT    - transfer count parameter
* DST    - destination address parameter
* IDX    - index parameter
* RLD    - count reload + link parameter
* QOPT   - QDMA options register
* QSRC   - QDMA source address register
* QCNT   - QDMA transfer count register
* QDST   - QDMA destination address register
* QIDX   - QDMA index register
* QSOPT  - QDMA options pseudo register
* QSSRC  - QDMA source address pseudo register
* QSCNT  - QDMA transfer count pseudo register
* QSDST  - QDMA destination address pseudo register
* QSIDX  - QDMA index pseudo register
* PQSR   - priority queue status register
* PQAR0  - priority queue allocation register 0
* PQAR1  - priority queue allocation register 1
* PQAR2  - priority queue allocation register 2
* PQAR3  - priority queue allocation register 3
CIPRL  .equ  0x01a0ffe4;- channel interrupt pending register, low half (1)
CIPRH  .equ  0x01a0ffa4;- channel interrupt pending register, high half (1)
CIERL  .equ  0x01a0ffe8;- channel interrupt enable register, low half (1)
CIERH  .equ  0x01a0ffa8;- channel interrupt enable register, high half (1)
CCERL  .equ  0x01a0ffec;- channel chain enable register, low half (1)
CCERH  .equ  0x01a0ffac;- channel chain enable register, high half (1)
ERL    .equ  0x01a0fff0;- event register, low half (1)
ERH    .equ  01a0ffb0h;- event register, high half (1)
EERL   .equ  01a0fff4h;- event enable register, low half (1)
EERH   .equ  01a0ffb4h;- event enable register, high half (1)
EPRL   .equ  01a0ffdch;- event polarity register, low half (1)
EPRH   .equ  01a0ff9ch;- event polarity register, high half (1)
ECRL   .equ  01a0fff8h;- event clear register, low half (1)
ECRH   .equ  01a0ffb8h;- event clear register, high half (1)
ESRL   .equ  01a0fffch;- event set register, low half (1)
ESRH   .equ  01a0ffbch;- event set register, high half (1)
vp1_y  .equ  01a00540h;-event set of opt src cnt src idx rld
vp1_link .equ  01a00630h;-event set of opt src cnt src idx rld
       .def  _edma_config
_edma_config:

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;           
           mvkl   EERH,a1
           mvkh   EERH,a1;使能video port is reset
           ;ldw    *a1,a2
           mvkl   0h,b1
           mvkh   0h,b1 
           nop    4     
          ; or     b1,a2,b1
           stw    b1,*a1;
           nop    9
           mvkl   EERL,a1
           mvkh   EERL,a1;使能video port is reset
           ;ldw    *a1,a2
           mvkl   0018h,b1
           mvkh   0h,b1 
           nop    4     
          ; or     b1,a2,b1
           stw    b1,*a1;
           nop    9
           ;;;;;;;;;;;;;;;;;;;;;;;
           mvkl   ECRH,a1
           mvkh   ECRH,a1;使能video port is reset
           ;ldw    *a1,a2
           mvkl   01000000h,b1
           mvkh   01000000h,b1 
           nop    4     
          ; or     b1,a2,b1
           stw    b1,*a1;
           nop    9
           mvkl   ECRL,a1
           mvkh   ECRL,a1;使能video port is reset
           ;ldw    *a1,a2
           mvkl   0h,b1
           mvkh   0h,b1 
           nop    4     
          ; or     b1,a2,b1
           stw    b1,*a1;
           nop    9
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;             
           mvkl   vp1_y,a1
           mvkh   vp1_y,a1;使能video port is reset
           ;ldw    *a1,a2
           mvkl   0h,b1
           mvkh   0h,b1 
           nop    4     
          ; or     b1,a2,b1
           stw    b1,*a1;
           add    a1,4,a1
           nop    5
           stw    b1,*a1;
           add    a1,4,a1
           nop    5 
           stw    b1,*a1;
           add    a1,4,a1
           nop    5
           stw    b1,*a1;
           add    a1,4,a1
           nop    5
           stw    b1,*a1;
           add    a1,4,a1
           nop    5
           stw    b1,*a1;
           add    a1,4,a1
           nop    5
           mvkl   vp1_link,a1
           mvkh   vp1_link,a1;使能video port is reset
           ;ldw    *a1,a2
           mvkl   0h,b1
           mvkh   0h,b1 
           nop    4     
          ; or     b1,a2,b1
           stw    b1,*a1;
           add    a1,4,a1
           nop    5
           stw    b1,*a1;
           add    a1,4,a1
           nop    5 
           stw    b1,*a1;
           add    a1,4,a1
           nop    5
           stw    b1,*a1;
           add    a1,4,a1
           nop    5
           stw    b1,*a1;
           add    a1,4,a1
           nop    5
           stw    b1,*a1;
           add    a1,4,a1
           nop    5


           ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;             
           mvkl   vp1_y,a1
           mvkh   vp1_y,a1;使能video port is reset
           ;ldw    *a1,a2
           mvkl   40b40002h,b1
           mvkh   40b40002h,b1 
           nop    4     
          ; or     b1,a2,b1
           stw    b1,*a1;
           nop    9;;;;;;;;;;;;;set opt
           add    a1,4,a1
           mvkl   78000000h,b1
           mvkh   78000000h,b1 
           nop    4     
          ; or     b1,a2,b1
           stw    b1,*a1;
           nop    9;;;;;;;;;;;;;set src
           add    a1,4,a1
           mvkl   023f00b4h,b1
           mvkh   023f00b4h,b1 
           nop    4     
          ; or     b1,a2,b1
           stw    b1,*a1;
           nop    9;;;;;;;;;;;;;set cnt
           add    a1,4,a1
           mvkl   80000000h,b1
           mvkh   80000000h,b1 
           nop    4     
          ; or     b1,a2,b1
           stw    b1,*a1;
           nop    9;;;;;;;;;;;;;set dst
           add    a1,4,a1
           mvkl   02d00000h,b1
           mvkh   02d00000h,b1 
           nop    4     
          ; or     b1,a2,b1
           stw    b1,*a1;
           nop    9;;;;;;;;;;;;;set idx
           add    a1,4,a1
           mvkl   00000630h,b1
           mvkh   00000630h,b1 
           nop    4     
          ; or     b1,a2,b1
           stw    b1,*a1;
           nop    9;;;;;;;;;;;;;
         ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
           mvkl   vp1_link,a1
           mvkh   vp1_link,a1;使能video port is reset
          ; ldw    *a1,a2
           mvkl   40b40002h,b1
           mvkh   40b40002h,b1 
           nop    4     
          ; or     b1,a2,b1
           stw    b1,*a1;
           nop    9;;;;;;;;;;;;;set opt
           add    a1,4,a1
           mvkl   78000000h,b1
           mvkh   78000000h,b1 
           nop    4     
          ; or     b1,a2,b1
           stw    b1,*a1;
           nop    9;;;;;;;;;;;;;set src
           add    a1,4,a1
           mvkl   023f00b4h,b1
           mvkh   023f00b4h,b1 
           nop    4     
          ; or     b1,a2,b1
           stw    b1,*a1;
           nop    9;;;;;;;;;;;;;set cnt
           add    a1,4,a1
           mvkl   80000000h,b1
           mvkh   80000000h,b1 
           nop    4     
          ; or     b1,a2,b1
           stw    b1,*a1;
           nop    9;;;;;;;;;;;;;set dst
           add    a1,4,a1
           mvkl   02d00000h,b1
           mvkh   02d00000h,b1 
           nop    4     
          ; or     b1,a2,b1
           stw    b1,*a1;
           nop    9;;;;;;;;;;;;;set idx
           add    a1,4,a1
           mvkl   00000630h,b1
           mvkh   00000630h,b1 
           nop    4     
          ; or     b1,a2,b1
           stw    b1,*a1;
           nop    9;;;;;;;;;;;;;
         ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;  
           mvkl   EERH,a1
           mvkh   EERH,a1;使能video port is reset
           ldw    *a1,a2
           mvkl   01000000h,b1
           mvkh   01000000h,b1 
           nop    4     
          ; or     b1,a2,b1
           stw    b1,*a1;
           nop    9;;;;;;;;;;;;;;;;;;;;;;;
           ;;;;;;;;;;;;