📄 vga_config.asm
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VDVINT1 .equ 0x01c44260 ;- Video Port 1 Video Display Vertical Interrupt
VDVINT2 .equ 0x01c48260 ;- Video Port 2 Video Display Vertical Interrupt
VDFBIT0 .equ 0x01c40264 ;- Video Port 0 Video Display Field Bit Register
VDFBIT1 .equ 0x01c44264 ;- Video Port 1 Video Display Field Bit Register
VDFBIT2 .equ 0x01c48264 ;- Video Port 2 Video Display Field Bit Register
VDVBIT10 .equ 0x01c40268 ;- Video Port 0 Video Display Vertical Blank Bit-Field 1 Register
VDVBIT11 .equ 0x01c44268 ;- Video Port 1 Video Display Vertical Blank Bit-Field 1 Register
VDVBIT12 .equ 0x01c48268 ;- Video Port 2 Video Display Vertical Blank Bit-Field 1 Register
VDVBIT20 .equ 0x01c4026c ;- Video Port 0 Video Display Vertical Blank Bit-Field 2 Register
VDVBIT21 .equ 0x01c4426c ;- Video Port 1 Video Display Vertical Blank Bit-Field 2 Register
VDVBIT22 .equ 0x01c4826c ;- Video Port 2 Video Display Vertical Blank Bit-Field 2 Register
*
********************************************************************************
* FIFO Mapping
*
YSRCA0 .equ 0x74000000 ;- Video Port 0 Y FIFO Source Register A
YSRCA1 .equ 0x78000000 ;- Video Port 1 Y FIFO Source Register A
YSRCA2 .equ 0x7c000000 ;- Video Port 2 Y FIFO Source Register A
CBSRCA0 .equ 0x74000008 ;- Video Port 0 Cb FIFO Source Register A
CBSRCA1 .equ 0x78000008 ;- Video Port 1 Cb FIFO Source Register A
CBSRCA2 .equ 0x7c000008 ;- Video Port 2 Cb FIFO Source Register A
CRSRCA0 .equ 0x74000010 ;- Video Port 0 Cr FIFO Source Register A
CRSRCA1 .equ 0x78000010 ;- Video Port 1 Cr FIFO Source Register A
CRSRCA2 .equ 0x7c000010 ;- Video Port 2 Cr FIFO Source Register A
YSRCB0 .equ 0x74000020 ;- Video Port 0 Y FIFO Source Register B (only for DM642)
YSRCB1 .equ 0x78000020 ;- Video Port 1 Y FIFO Source Register B (only for DM642)
YSRCB2 .equ 0x7c000020 ;- Video Port 2 Y FIFO Source Register B (only for DM642)
CBSRCB0 .equ 0x74000028 ;- Video Port 0 Cb FIFO Source Register B (only for DM642)
CBSRCB1 .equ 0x78000028 ;- Video Port 1 Cb FIFO Source Register B (only for DM642)
CBSRCB2 .equ 0x7c000028 ;- Video Port 2 Cb FIFO Source Register B (only for DM642)
CRSRCB0 .equ 0x74000030 ;- Video Port 0 Cr FIFO Source Register B (only for DM642)
CRSRCB1 .equ 0x78000030 ;- Video Port 1 Cr FIFO Source Register B (only for DM642)
CRSRCB2 .equ 0x7c000030 ;- Video Port 2 Cr FIFO Source Register B (only for DM642)
YDSTA0 .equ 0x76000000 ;- Video Port 0 Y FIFO Destination Register A
YDSTA1 .equ 0x7a000000 ;- Video Port 1 Y FIFO Destination Register A
YDSTA2 .equ 0x7e000000 ;- Video Port 2 Y FIFO Destination Register A
CBDST0 .equ 0x76000008 ;- Video Port 0 Cb FIFO Destination Register
CBDST1 .equ 0x7a000008 ;- Video Port 1 Cb FIFO Destination Register
CBDST2 .equ 0x7e000008 ;- Video Port 2 Cb FIFO Destination Register
CRDST0 .equ 0x76000010 ;- Video Port 0 Cr FIFO Destination Register
CRDST1 .equ 0x7a000010 ;- Video Port 1 Cr FIFO Destination Register
CRDST2 .equ 0x7e000010 ;- Video Port 2 Cr FIFO Destination Register
YDSTB0 .equ 0x76000020 ;- Video Port 0 Y FIFO Destination Register B (only for DM642)
YDSTB1 .equ 0x7a000020 ;- Video Port 1 Y FIFO Destination Register B (only for DM642)
YDSTB2 .equ 0x7e000020 ;- Video Port 2 Y FIFO Destination Register B (only for DM642)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
MVC.S2 CSR,B4
MVC.S2 CSR,B5
;or.D2 1,B4,B4
; AND.D2 -2,B5,B5
; MVC.S2 B4,CSR
;mvc ier,b4
; or
.def vga_cog
mvkl VPCTL1,a1
mvkh VPCTL1,a1;使能video port is reset
ldw *a1,a2
mvkl 8000h,b1
mvkh 8000h,b1
nop 4
or b1,a2,b1
; stw b1,*a1;
nop 9;;;;;;;;;;;;;;;;;;;;;;;
mvkl 02000h,b1
mvkh 0h,b1
bdec $,b1
; stw b1,*a1;
nop 9;;;;;;;;;;;;;;;;;;;;;;;
vga_cog: nop 9
nop 9
ldw *a1,a2
mvkl 4000h,b1
mvkh 4000h,b1
nop 2
and b1,a2,b1
; [!b1] b vga_cog
nop 9
mvkl PCR1,a1
mvkh PCR1,a1;使能video port is enabled
ldw *a1,a2
mvkl 05h,b1
mvkh 0,b1
or b1,a2,b1
stw b1,*a1;
nop ;;;;;;;;;;;;;;;;;;;;;;; nop
nop
mvkl VPIE1,a1
mvkh VPIE1,a1;使能video port interrupt is enable
ldw *a1,a2
mvkl 004fh,b1
mvkh 004fh,b1
; or b1,a2,b1
nop 4
stw b1,*a1;
nop 9;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
mvkl VCACTL1,a1
mvkh VCACTL1,a1;video port pin direction register
ldw *a1,a2
; mvkl 40080840h,b1
nop 4
; mvkh 40080840h,b1
clr a2,11,11,a2
set a2,11,11,a2
stw a2,*a1;
nop ;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
mvkl VCASTRT11,a1
mvkh VCASTRT11,a1;video port pin direction register
ldw *a1,a2
mvkl 01008Eh,b1
mvkh 01008eh,b1
or b1,a2,b1
stw b1,*a1;
nop ;;;;;;;;;;;;;;;;;;;;;;;
mvkl VCASTOP11,a1
mvkh VCASTOP11,a1;video port pin direction register
ldw *a1,a2
mvkl 0120035Dh,b1
mvkh 0120035dh,b1
or b1,a2,b1
stw b1,*a1;
nop ;;;;;;;;;;;;;;;;;;;;;;;
mvkl VCASTRT21,a1
mvkh VCASTRT12,a1;video port pin direction register
ldw *a1,a2
mvkl 01808Eh,b1
mvkh 01808eh,b1
or b1,a2,b1
stw b1,*a1;
nop ;;;;;;;;;;;;;;;;;;;;;;;
mvkl VCASTOP21,a1
mvkh VCASTOP12,a1;video port pin direction register
ldw *a1,a2
mvkl 0120035Dh,b1
mvkh 0120035dh,b1
or b1,a2,b1
stw b1,*a1;
nop ;;;;;;;;;;;;;;;;;;;;;;;
mvkl VCATHRLD1,a1
mvkh VCATHRLD1,a1;video port pin direction register
ldw *a1,a2
mvkl 005a005Ah,b1
mvkh 005A005ah,b1
or b1,a2,b1
stw b1,*a1;
nop ;;;;;;;;;;;;;;;;;;;;;;;
mvkl VCAEVTCT1,a1
mvkh VCAEVTCT1,a1;video port pin direction register
ldw *a1,a2
mvkl 01200120h,b1
mvkh 01200120h,b1
or b1,a2,b1
stw b1,*a1;
nop ;;;;;;;;;;;;;;;;;;;;;;;
mvkl VCACTL1,a1
mvkh VCACTL1,a1;video port pin direction register
ldw *a1,a2
mvkl 0fffffff8h,b1
mvkh 0fffffff8h,b1
and b1,a2,a2
nop 4
stw a2,*a1;
nop ;;;;;;;;;;;;;;;;;;;;;;;
mvkl VCACTL1,a1
mvkh VCACTL1,a1;video port pin direction register
ldw *a1,a2
nop 4
clr a2,7,7,a2
stw a2,*a1;
nop 4
clr a2,6,6,a2
set a2,6,6,a2
stw a2,*a1;
nop 4
clr a2,5,5,a2
stw a2,*a1
nop 4
clr a2,4,4,a2
stw a2,*a1
nop 4
clr a2,17,17,a2
set a2,17,17,a2
stw a2,*a1
nop 4
clr a2,16,16,a2
stw a2,*a1
nop 4
nop ;;;;;;;;;;;;;;;;;;;;;;;
nop 9
mvkl VPCTL1,a1
mvkh VPCTL1,a1;使能video port is reset
ldw *a1,a2
mvkl 4000h,b1
mvkh 4000h,b1
nop 4
or b1,a2,b1
stw b1,*a1;
nop 9;;;;;;;;;;;;;;;;;;;;;;;
mvkl VCACTL1,a1
mvkh VCACTL1,a1;video port pin direction register
ldw *a1,a2
nop 4
clr a2,15,15,a2
set a2,15,15,a2
stw a2,*a1;
nop 4
nop ;;;;;;;;;;;;;;;;;;;;;;;
clr a2,30,30,a2
stw a2,*a1
nop 4
nop 9
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