vga_config.asm

在DM642硬件平台上

VPPID0    .equ 0x01c40000  ;  Video Port 0 Peripheral Identification Register
VPPID1    .equ 0x01c44000  ;  Video Port 1 Peripheral Identification Register
VPPID2    .equ 0x01c48000  ;  Video Port 2 Peripheral Identification Register
PCR0      .equ 0x01c40004  ;  Video Port 0 Peripheral Control                    
PCR1      .equ 0x01c44004  ;  Video Port 1 Peripheral Control
PCR2      .equ 0x01c48004  ;  Video Port 2 Peripheral Control
PFUNC0    .equ 0x01c40020  ;  Video Port 0 Pin Function
PFUNC1    .equ 0x01c44020  ;  Video Port 1 Pin Function
PFUNC2    .equ 0x01c48020  ;  Video Port 2 Pin Function
PDIR0     .equ 0x01c40024  ;  Video Port 0 Pin Direction
PDIR1     .equ 0x01c44024  ;  Video Port 1 Pin Direction
PDIR2     .equ 0x01c48024  ;  Video Port 2 Pin Direction
PDIN0     .equ 0x01c40028  ;  Video Port 0 Pin Data In
PDIN1     .equ 0x01c44028  ;  Video Port 1 Pin Data In
PDIN2     .equ 0x01c48028  ;  Video Port 2 Pin Data In
PDOUT0    .equ 0x01c4002c  ;  Video Port 0 Pin Data Out
PDOUT1    .equ 0x01c4402c  ;  Video Port 1 Pin Data Out
PDOUT2    .equ 0x01c4802c  ;  Video Port 2 Pin Data Out
PDSET0    .equ 0x01c40030  ;  Video Port 0 Pin Data Set
PDSET1    .equ 0x01c44030  ;  Video Port 1 Pin Data Set
PDSET2    .equ 0x01c48030  ;  Video Port 2 Pin Data Set
PDCLR0    .equ 0x01c40034  ;  Video Port 0 Pin Data Clear
PDCLR1    .equ 0x01c44034  ;  Video Port 1 Pin Data Clear
PDCLR2    .equ 0x01c48034  ;  Video Port 2 Pin Data Clear
PIEN0     .equ 0x01c40038  ;  Video Port 0 Pin Interrupt Enable
PIEN1     .equ 0x01c44038  ;  Video Port 1 Pin Interrupt Enable
PIEN2     .equ 0x01c48038  ;  Video Port 2 Pin Interrupt Enable
PIPOL0    .equ 0x01c4003c  ;  Video Port 0 Pin Interrupt Polarity
PIPOL1    .equ 0x01c4403c  ;  Video Port 1 Pin Interrupt Polarity
PIPOL2    .equ 0x01c4803c  ;  Video Port 2 Pin Interrupt Polarity
PISTAT0   .equ 0x01c40040  ;  Video Port 0 Pin Interrupt Status
PISTAT1   .equ 0x01c44040  ;  Video Port 1 Pin Interrupt Status
PISTAT2   .equ 0x01c48040  ;  Video Port 2 Pin Interrupt Status
PICLR0    .equ 0x01c40044  ;  Video Port 0 Pin Interrupt Clear
PICLR1    .equ 0x01c44044  ;  Video Port 1 Pin Interrupt Clear
PICLR2    .equ 0x01c48044  ;  Video Port 2 Pin Interrupt Clear
VPCTL0    .equ 0x01c400c0  ;  Video Port 0 Control Register
VPCTL1    .equ 0x01c440c0  ;  Video Port 1 Control Register
VPCTL2    .equ 0x01c480c0  ;  Video Port 2 Control Register
VPSTAT0   .equ 0x01c400c4  ;  Video Port 0 Status Register	
VPSTAT1   .equ 0x01c440c4  ;  Video Port 1 Status Register	
VPSTAT2   .equ 0x01c480c4  ;  Video Port 2 Status Register	
VPIE0     .equ 0x01c400c8  ;  Video Port 0 Interrupt Enable Register
VPIE1     .equ 0x01c440c8  ;  Video Port 1 Interrupt Enable Register
VPIE2     .equ 0x01c480c8  ;  Video Port 2 Interrupt Enable Register
VPIS0     .equ 0x01c400cc  ;  Video Port 0 Interrupt Status Register
VPIS1     .equ 0x01c440cc  ;  Video Port 1 Interrupt Status Register
VPIS2     .equ 0x01c480cc  ;  Video Port 2 Interrupt Status Register
********************************************************************************
* Memory Mapping Register -- Capture
*
VCASTAT0  .equ 0x01c40100  ;  Video Port 0 Video Capture A Status
VCASTAT1  .equ 0x01c44100  ;  Video Port 1 Video Capture A Status
VCASTAT2  .equ 0x01c48100  ;  Video Port 2 Video Capture A Status
VCACTL0   .equ 0x01c40104  ;  Video Port 0 Video Capture A Control
VCACTL1   .equ 0x01c44104  ;  Video Port 1 Video Capture A Control
VCACTL2   .equ 0x01c48104  ;  Video Port 2 Video Capture A Control
VCASTRT10 .equ 0x01c40108  ;  Video Port 0 Video Capture A Field1 Start
VCASTRT11 .equ 0x01c44108  ;  Video Port 1 Video Capture A Field1 Start
VCASTRT12 .equ 0x01c48108  ;  Video Port 2 Video Capture A Field1 Start
VCASTOP10 .equ 0x01c4010c  ;  Video Port 0 Video Capture A Field1 Stop
VCASTOP11 .equ 0x01c4410c  ;  Video Port 1 Video Capture A Field1 Stop
VCASTOP12 .equ 0x01c4810c  ;  Video Port 2 Video Capture A Field1 Stop
VCASTRT20 .equ 0x01c40110  ;  Video Port 0 Video Capture A Field2 Start
VCASTRT21 .equ 0x01c44110  ;  Video Port 1 Video Capture A Field2 Start
VCASTRT22 .equ 0x01c48110  ;  Video Port 2 Video Capture A Field2 Start
VCASTOP20 .equ 0x01c40114  ;  Video Port 0 Video Capture A Field2 Stop
VCASTOP21 .equ 0x01c44114  ;  Video Port 1 Video Capture A Field2 Stop
VCASTOP22 .equ 0x01c48114  ;  Video Port 2 Video Capture A Field2 Stop
VCAVINT0  .equ 0x01c40118  ;  Video Port 0 Video Capture A Vertical Interrupt
VCAVINT1  .equ 0x01c44118  ;  Video Port 1 Video Capture A Vertical Interrupt
VCAVINT2  .equ 0x01c48118  ;  Video Port 2 Video Capture A Vertical Interrupt
VCATHRLD0 .equ 0x01c4011c  ;  Video Port 0 Video Capture A Threshold
VCATHRLD1 .equ 0x01c4411c  ;  Video Port 1 Video Capture A Threshold
VCATHRLD2 .equ 0x01c4811c  ;  Video Port 2 Video Capture A Threshold
VCAEVTCT0 .equ 0x01c40120  ;  Video Port 0 Video Capture A Event Count
VCAEVTCT1 .equ 0x01c44120  ;  Video Port 1 Video Capture A Event Count
VCAEVTCT2 .equ 0x01c48120  ;  Video Port 2 Video Capture A Event Count
*
VCBSTAT0  .equ 0x01c40140  ;  Video Port 0 Video Capture B Status (only for DM642)
VCBSTAT1  .equ 0x01c44140  ;  Video Port 1 Video Capture B Status (only for DM642)
VCBSTAT2  .equ 0x01c48140  ;  Video Port 2 Video Capture B Status (only for DM642)
VCBCTL0   .equ 0x01c40144  ;  Video Port 0 Video Capture B Control (only for DM642)
VCBCTL1   .equ 0x01c44144  ;  Video Port 1 Video Capture B Control (only for DM642)
VCBCTL2   .equ 0x01c48144  ;  Video Port 2 Video Capture B Control (only for DM642)
VCBSTRT10 .equ 0x01c40148  ;  Video Port 0 Video Capture B Field1 Start (only for DM642)
VCBSTRT11 .equ 0x01c44148  ;  Video Port 1 Video Capture B Field1 Start (only for DM642)
VCBSTRT12 .equ 0x01c48148  ;  Video Port 2 Video Capture B Field1 Start (only for DM642)
VCBSTOP10 .equ 0x01c4014c  ;  Video Port 0 Video Capture B Field1Stop (only for DM642)
VCBSTOP11 .equ 0x01c4414c  ;  Video Port 1 Video Capture B Field1Stop (only for DM642)
VCBSTOP12 .equ 0x01c4814c  ;  Video Port 2 Video Capture B Field1Stop (only for DM642)
VCBSTRT20 .equ 0x01c40150  ;  Video Port 0 Video Capture B Field2 Start (only for DM642)
VCBSTRT21 .equ 0x01c44150  ;  Video Port 1 Video Capture B Field2 Start (only for DM642)
VCBSTRT22 .equ 0x01c48150  ;  Video Port 2 Video Capture B Field2 Start (only for DM642)
VCBSTOP20 .equ 0x01c40154  ;  Video Port 0 Video Capture B Field2Stop (only for DM642)
VCBSTOP21 .equ 0x01c44154  ;  Video Port 1 Video Capture B Field2Stop (only for DM642)
VCBSTOP22 .equ 0x01c48154  ;  Video Port 2 Video Capture B Field2Stop (only for DM642)
VCBVINT0  .equ 0x01c40158  ;  Video Port 0 Video Capture B Vertical Interrupt (only for DM642)
VCBVINT1  .equ 0x01c44158  ;  Video Port 1 Video Capture B Vertical Interrupt (only for DM642)
VCBVINT2  .equ 0x01c48158  ;  Video Port 2 Video Capture B Vertical Interrupt (only for DM642)
VCBTHRLD0 .equ 0x01c4015c  ;  Video Port 0 Video Capture B Threshold (only for DM642)
VCBTHRLD1 .equ 0x01c4415c  ;  Video Port 1 Video Capture B Threshold (only for DM642)
VCBTHRLD2 .equ 0x01c4815c  ;  Video Port 2 Video Capture B Threshold (only for DM642)
VCBEVTCT0 .equ 0x01c40160  ;  Video Port 0 Video Capture B Event Count (only for DM642)
VCBEVTCT1 .equ 0x01c44160  ;  Video Port 1 Video Capture B Event Count (only for DM642)
VCBEVTCT2 .equ 0x01c48160  ; Video Port 2 Video Capture B Event Count (only for DM642)
*
TSICTL0      .equ 0x01c40180  ;-  Video Port 0 Transport Stream Interface Capture Control
TSICTL1      .equ 0x01c44180  ;-  Video Port 1 Transport Stream Interface Capture Control
TSICTL2      .equ 0x01c48180  ;-  Video Port 2 Transport Stream Interface Capture Control
TSICLKINITL0 .equ 0x01c40184  ;-  Video Port 0 Transport Stream Interface Clock Initialization LSB
TSICLKINITL1 .equ 0x01c44184  ;-  Video Port 1 Transport Stream Interface Clock Initialization LSB
TSICLKINITL2 .equ 0x01c48184  ;-  Video Port 2 Transport Stream Interface Clock Initialization LSB
TSICLKINITM0 .equ 0x01c40188  ;-  Video Port 0 Transport Stream Interface Clock Initialization MSB
TSICLKINITM1 .equ 0x01c44188  ;-  Video Port 1 Transport Stream Interface Clock Initialization MSB
TSICLKINITM2 .equ 0x01c48188  ;-  Video Port 2 Transport Stream Interface Clock Initialization MSB
TSISTCLKL0   .equ 0x01c4018c  ;-  Video Port 0 Transport Stream Interface System Time Clock LSB
TSISTCLKL1   .equ 0x01c4418c  ;-  Video Port 1 Transport Stream Interface System Time Clock LSB
TSISTCLKL2   .equ 0x01c4818c  ;-  Video Port 2 Transport Stream Interface System Time Clock LSB
TSISTCLKM0   .equ 0x01c40190  ;-  Video Port 0 Transport Stream Interface System Time Clock  MSB
TSISTCLKM1   .equ 0x01c44190  ;-  Video Port 1 Transport Stream Interface System Time Clock  MSB
TSISTCLKM2   .equ 0x01c48190  ;-  Video Port 2 Transport Stream Interface System Time Clock  MSB
TSISTCMPL0   .equ 0x01c40194  ;-  Video Port 0 Transport Stream Interface STC Compare LSB
TSISTCMPL1   .equ 0x01c44194  ;-  Video Port 1 Transport Stream Interface STC Compare LSB
TSISTCMPL2   .equ 0x01c48194  ;-  Video Port 2 Transport Stream Interface STC Compare LSB
TSISTCMPM0   .equ 0x01c40198  ;-  Video Port 0 Transport Stream Interface STC Compare MSB
TSISTCMPM1   .equ 0x01c44198  ;-  Video Port 1 Transport Stream Interface STC Compare MSB
TSISTCMPM2   .equ 0x01c48198  ;-  Video Port 2 Transport Stream Interface STC Compare MSB
TSISTMSKL0   .equ 0x01c4019c  ;-  Video Port 0 Transport Stream Interface STC Compare Mask LSB
TSISTMSKL1   .equ 0x01c4419c  ;-  Video Port 1 Transport Stream Interface STC Compare Mask LSB
TSISTMSKL2   .equ 0x01c4819c  ;-  Video Port 2 Transport Stream Interface STC Compare Mask LSB
TSISTMSKM0   .equ 0x01c401a0  ;-  Video Port 0 Transport Stream Interface STC Compare Mask MSB
TSISTMSKM1   .equ 0x01c441a0  ;-  Video Port 1 Transport Stream Interface STC Compare Mask MSB
TSISTMSKM2   .equ 0x01c481a0  ;-  Video Port 2 Transport Stream Interface STC Compare Mask MSB
TSITICKS0    .equ 0x01c401a4  ;-  Video Port 0 Transport Stream Interface STC Ticks Interrupt
TSITICKS1    .equ 0x01c441a4  ;-  Video Port 1 Transport Stream Interface STC Ticks Interrupt
TSITICKS2    .equ 0x01c481a4  ;-  Video Port 2 Transport Stream Interface STC Ticks Interrupt
*
********************************************************************************
* Memory Mapping Register -- Display
*
* (DM640 has only one video port, i.e. only Port 0 registers are valid)
* (DM641 has only two video ports, i.e. only Port 0 and Port 1 registers are valid)
* (DM642 has three video ports, i.e. Port 0, Port 1 and Port 2)
*
VDSTAT0      .equ 0x01c40200  ;-  Video Port 0 Video Display Status
VDSTAT1      .equ 0x01c44200  ;-  Video Port 1 Video Display Status
VDSTAT2      .equ 0x01c48200  ;-  Video Port 2 Video Display Status
VDCTL0       .equ 0x01c40204  ;-  Video Port 0 Video Display Control
VDCTL1       .equ 0x01c44204  ;-  Video Port 1 Video Display Control
VDCTL2       .equ 0x01c48204  ;-  Video Port 2 Video Display Control
VDFRMSZ0     .equ 0x01c40208  ;-  Video Port 0 Video Display Frame Size
VDFRMSZ1     .equ 0x01c44208  ;-  Video Port 1 Video Display Frame Size
VDFRMSZ2     .equ 0x01c48208  ;-  Video Port 2 Video Display Frame Size
VDHBLNK0     .equ 0x01c4020c  ;-  Video Port 0 Video Display Horizontal Blanking
VDHBLNK1     .equ 0x01c4420c  ;-  Video Port 1 Video Display Horizontal Blanking
VDHBLNK2     .equ 0x01c4820c  ;-  Video Port 2 Video Display Horizontal Blanking
VDVBLKS10    .equ 0x01c40210  ;-  Video Port 0 Video Display Vertical Blanking Start - Field 1
VDVBLKS11    .equ 0x01c44210  ;-  Video Port 1 Video Display Vertical Blanking Start - Field 1
VDVBLKS12    .equ 0x01c48210  ;-  Video Port 2 Video Display Vertical Blanking Start - Field 1
VDVBLKE10    .equ 0x01c40214  ;-  Video Port 0 Video Display Vertical Blanking End - Field 1
VDVBLKE11    .equ 0x01c44214  ;-  Video Port 1 Video Display Vertical Blanking End - Field 1
VDVBLKE12    .equ 0x01c48214  ;-  Video Port 2 Video Display Vertical Blanking End - Field 1
VDVBLKS20    .equ 0x01c40218  ;-  Video Port 0 Video Display Vertical Blanking Start - Field 2
VDVBLKS21    .equ 0x01c44218  ;-  Video Port 1 Video Display Vertical Blanking Start - Field 2
VDVBLKS22    .equ 0x01c48218  ;-  Video Port 2 Video Display Vertical Blanking Start - Field 2
VDVBLKE20    .equ 0x01c4021c  ;-  Video Port 0 Video Display Vertical Blanking End - Field 2
VDVBLKE21    .equ 0x01c4421c  ;-  Video Port 1 Video Display Vertical Blanking End - Field 2
VDVBLKE22    .equ 0x01c4821c  ;-  Video Port 2 Video Display Vertical Blanking End - Field 2
VDIMGOFF10   .equ 0x01c40220  ;-  Video Port 0 Video Display Image Offset - Field 1
VDIMGOFF11   .equ 0x01c44220  ;-  Video Port 1 Video Display Image Offset - Field 1
VDIMGOFF12   .equ 0x01c48220  ;-  Video Port 2 Video Display Image Offset - Field 1
VDIMGSZ10    .equ 0x01c40224  ;-  Video Port 0 Video Display Image Size - Field 1
VDIMGSZ11    .equ 0x01c44224  ;-  Video Port 1 Video Display Image Size - Field 1
VDIMGSZ12    .equ 0x01c48224  ;-  Video Port 2 Video Display Image Size - Field 1
VDIMGOFF20   .equ 0x01c40228  ;-  Video Port 0 Video Display Image Offset - Field 2
VDIMGOFF21   .equ 0x01c44228  ;-  Video Port 1 Video Display Image Offset - Field 2
VDIMGOFF22   .equ 0x01c48228  ;-  Video Port 2 Video Display Image Offset - Field 2
VDIMGSZ20    .equ 0x01c4022c  ;-  Video Port 0 Video Display Image Size - Field 2
VDIMGSZ21    .equ 0x01c4422c  ;-  Video Port 1 Video Display Image Size - Field 2
VDIMGSZ22    .equ 0x01c4822c  ;-  Video Port 2 Video Display Image Size - Field 2
VDFLDT10     .equ 0x01c40230  ;-  Video Port 0 Video Display Field1 Timing
VDFLDT11     .equ 0x01c44230  ;-  Video Port 1 Video Display Field1 Timing
VDFLDT12     .equ 0x01c48230  ;-  Video Port 2 Video Display Field1 Timing
VDFLDT20     .equ 0x01c40234  ;-  Video Port 0 Video Display Field2 Timing
VDFLDT21     .equ 0x01c44234  ;-  Video Port 1 Video Display Field2 Timing
VDFLDT22     .equ 0x01c48234  ;-  Video Port 2 Video Display Field2 Timing
VDTHRLD0     .equ 0x01c40238  ;-  Video Port 0 Video Display Threshold
VDTHRLD1     .equ 0x01c44238  ;-  Video Port 1 Video Display Threshold
VDTHRLD2     .equ 0x01c48238  ;-  Video Port 2 Video Display Threshold
VDHSYNC0     .equ 0x01c4023c  ;-  Video Port 0 Video Display Horizontal Sync
VDHSYNC1     .equ 0x01c4423c  ;-  Video Port 1 Video Display Horizontal Sync
VDHSYNC2     .equ 0x01c4823c  ;-  Video Port 2 Video Display Horizontal Sync
VDVSYNS10    .equ 0x01c40240  ;-  Video Port 0 Video Display Vertical Synchronization Start - Field 1
VDVSYNS11    .equ 0x01c44240  ;-  Video Port 1 Video Display Vertical Synchronization Start - Field 1
VDVSYNS12    .equ 0x01c48240  ;-  Video Port 2 Video Display Vertical Synchronization Start - Field 1
VDVSYNE10    .equ 0x01c40244  ;-  Video Port 0 Video Display Vertical Synchronization End - Field 1
VDVSYNE11    .equ 0x01c44244  ; - Video Port 1 Video Display Vertical Synchronization End - Field 1
VDVSYNE12    .equ 0x01c48244  ;-  Video Port 2 Video Display Vertical Synchronization End - Field 1
VDVSYNS20    .equ 0x01c40248  ;-  Video Port 0 Video Display Vertical Synchronization Start - Field 2
VDVSYNS21    .equ 0x01c44248  ;-  Video Port 1 Video Display Vertical Synchronization Start - Field 2
VDVSYNS22    .equ 0x01c48248  ;-  Video Port 2 Video Display Vertical Synchronization Start - Field 2
VDVSYNE20    .equ 0x01c4024c  ;-  Video Port 0 Video Display Vertical Synchronization End - Field 2
VDVSYNE21    .equ 0x01c4424c  ;-  Video Port 1 Video Display Vertical Synchronization End - Field 2
VDVSYNE22    .equ 0x01c4824c  ;-  Video Port 2 Video Display Vertical Synchronization End - Field 2
VDRELOAD0    .equ 0x01c40250  ;-  Video Port 0 Video Display Counter Reload
VDRELOAD1    .equ 0x01c44250  ;-  Video Port 1 Video Display Counter Reload
VDRELOAD2    .equ 0x01c48250  ;-  Video Port 2 Video Display Counter Reload
VDDISPEVT0   .equ 0x01c40254  ;-  Video Port 0 Video Display Display Event Register
VDDISPEVT1   .equ 0x01c44254  ;-  Video Port 1 Video Display Display Event Register
VDDISPEVT2   .equ 0x01c48254  ;-  Video Port 2 Video Display Display Event Register
VDCLIP0      .equ 0x01c40258  ;-  Video Port 0 Video Display Clipping Register
VDCLIP1      .equ 0x01c44258  ;-  Video Port 1 Video Display Clipping Register
VDCLIP2      .equ 0x01c48258  ;-  Video Port 2 Video Display Clipping Register
VDDEFVAL0    .equ 0x01c4025c  ;-  Video Port 0 Video Display Default Display Value
VDDEFVAL1    .equ 0x01c4425c  ;-  Video Port 1 Video Display Default Display Value
VDDEFVAL2    .equ 0x01c4825c  ;-  Video Port 2 Video Display Default Display Value
VDVINT0      .equ 0x01c40260  ;-  Video Port 0 Video Display Vertical Interrupt