📄 f2407_c.h
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#define MSGID5H (*(PORT)0x7229) /* CAN message ID for mailbox 5 (upper 16 bits) */
#define MSGCTRL5 (*(PORT)0x722A) /* CAN RTR and DLC for mailbox 5 */
#define MBX5A (*(PORT)0x722C) /* CAN 2 of 8 bytes of mailbox 5 */
#define MBX5B (*(PORT)0x722D) /* CAN 2 of 8 bytes of mailbox 5 */
#define MBX5C (*(PORT)0x722E) /* CAN 2 of 8 bytes of mailbox 5 */
#define MBX5D (*(PORT)0x722F) /* CAN 2 of 8 bytes of mailbox 5 */
/* Event Manager A (EVA) registers */
#define GPTCONA (*(PORT)0x7400) /* GP timer control reg A */
#define T1CNT (*(PORT)0x7401) /* GP timer 1 counter reg */
#define T1CMPR (*(PORT)0x7402) /* GP timer 1 compare reg */
#define T1PR (*(PORT)0x7403) /* GP timer 1 period reg */
#define T1CON (*(PORT)0x7404) /* GP timer 1 control reg */
#define T2CNT (*(PORT)0x7405) /* GP timer 2 counter reg */
#define T2CMPR (*(PORT)0x7406) /* GP timer 2 compare reg */
#define T2PR (*(PORT)0x7407) /* GP timer 2 period reg */
#define T2CON (*(PORT)0x7408) /* GP timer 2 control reg */
#define COMCONA (*(PORT)0x7411) /* Compare control reg A */
#define ACTRA (*(PORT)0x7413) /* Compare action control reg A */
#define DBTCONA (*(PORT)0x7415) /* Dead-band timer control reg A */
#define CMPR1 (*(PORT)0x7417) /* compare reg 1 */
#define CMPR2 (*(PORT)0x7418) /* compare reg 2 */
#define CMPR3 (*(PORT)0x7419) /* compare reg 3 */
#define CAPCONA (*(PORT)0x7420) /* Capture control reg A */
#define CAPFIFOA (*(PORT)0x7422) /* Capture FIFO status reg A */
#define CAP1FIFO (*(PORT)0x7423) /* Capture Channel 1 FIFO top */
#define CAP2FIFO (*(PORT)0x7424) /* Capture Channel 2 FIFO top */
#define CAP3FIFO (*(PORT)0x7425) /* Capture Channel 3 FIFO top */
#define CAP1FBOT (*(PORT)0x7427) /* Bottom reg of capture FIFO stack 1 */
#define CAP2FBOT (*(PORT)0x7428) /* Bottom reg of capture FIFO stack 2 */
#define CAP3FBOT (*(PORT)0x7429) /* Bottom reg of capture FIFO stack 3 */
#define EVAIMRA (*(PORT)0x742C) /* EVA interrupt mask reg A */
#define EVAIMRB (*(PORT)0x742D) /* EVA interrupt mask reg B */
#define EVAIMRC (*(PORT)0x742E) /* EVA interrupt mask reg C */
#define EVAIFRA (*(PORT)0x742F) /* EVA interrupt flag reg A */
#define EVAIFRB (*(PORT)0x7430) /* EVA interrupt flag reg B */
#define EVAIFRC (*(PORT)0x7431) /* EVA interrupt flag reg C */
/* Event Manager B (EVB) registers */
#define GPTCONB (*(PORT)0x7500) /* GP timer control reg B */
#define T3CNT (*(PORT)0x7501) /* GP timer 3 counter reg */
#define T3CMPR (*(PORT)0x7502) /* GP timer 3 compare reg */
#define T3PR (*(PORT)0x7503) /* GP timer 3 period reg */
#define T3CON (*(PORT)0x7504) /* GP timer 3 control reg */
#define T4CNT (*(PORT)0x7505) /* GP timer 4 counter reg */
#define T4CMPR (*(PORT)0x7506) /* GP timer 4 compare reg */
#define T4PR (*(PORT)0x7507) /* GP timer 4 period reg */
#define T4CON (*(PORT)0x7508) /* GP timer 4 control reg */
#define COMCONB (*(PORT)0x7511) /* Compare control register B */
#define ACTRB (*(PORT)0x7513) /* Compare action control register B */
#define DBTCONB (*(PORT)0x7515) /* Dead-band timer control reg B */
#define CMPR4 (*(PORT)0x7517) /* Compare reg 4 */
#define CMPR5 (*(PORT)0x7518) /* Compare reg 5 */
#define CMPR6 (*(PORT)0x7519) /* Compare reg 6 */
#define CAPCONB (*(PORT)0x7520) /* Capture control reg B */
#define CAPFIFOB (*(PORT)0x7522) /* Capture FIFO status reg B */
#define CAP4FIFO (*(PORT)0x7523) /* Capture channel 4 FIFO top */
#define CAP5FIFO (*(PORT)0x7524) /* Capture channel 5 FIFO top */
#define CAP6FIFO (*(PORT)0x7525) /* Capture channel 6 FIFO top */
#define CAP4FBOT (*(PORT)0x7527) /* Bottom reg of capture FIFO stack 4 */
#define CAP5FBOT (*(PORT)0x7528) /* Bottom reg of capture FIFO stack 5 */
#define CAP6FBOT (*(PORT)0x7529) /* Bottom reg of capture FIFO stack 6 */
#define EVBIMRA (*(PORT)0x752C) /* EVB interrupt mask reg A */
#define EVBIMRB (*(PORT)0x752D) /* EVB interrupt mask reg B */
#define EVBIMRC (*(PORT)0x752E) /* EVB interrupt mask reg C */
#define EVBIFRA (*(PORT)0x752F) /* EVB interrupt flag reg A */
#define EVBIFRB (*(PORT)0x7530) /* EVB interrupt flag reg B */
#define EVBIFRC (*(PORT)0x7531) /* EVB interrupt flag reg C */
/* I/O space mapped registers */
#define FCMR portFF0F /* Flash control mode register */
ioport unsigned int portFF0F; /* C2xx compiler specific keyword */
#define WSGR portFFFF /* Wait-state generator reg */
ioport unsigned int portFFFF; /* C2xx compiler specific keyword */
/*-------------------IOPA3/CAP1/QEP0*/
/*使能通用或特殊功能管脚宏*/
#define ENABLE_IOPA3_PIN OCRA &=~0X0008;
#define DISABLE_IOPA3_PIN OCRA |= 0X0008;
#define ENABLE_CAP1_PIN DISABLE_IOPA3_PIN;
#define DISABLE_CAP1_PIN ENABLE_IOPA3_PIN;
#define ENABLE_QEP0_PIN DISABLE_IOPA3_PIN;
#define DISABLE_QEP0_PIN ENABLE_IOPA3_PIN;
/*设置通用管脚为输出并设置电瓶宏*/
#define ENABLE_IOPA3_OUTPIN {ENABLE_IOPA3_PIN; PADATDIR |= 0X0800;}
#define SET_IOPA3_OUTPIN {ENABLE_IOPA3_OUTPIN; PADATDIR |= 0X0008;}
#define CLR_IOPA3_OUTPIN {ENABLE_IOPA3_OUTPIN; PADATDIR &=~0X0008;}
#define SWITCH_IOPA3_OUTPIN {ENABLE_IOPA3_OUTPIN; PADATDIR ^= 0X0008;}
/*设置通用管脚为输入并读状态宏*/
#define ENABLE_IOPA3_INPIN {ENABLE_IOPA3_PIN; PADATDIR &=~0X0800;}
#define READ_IOPA3_INPIN(var) {var = PADATDIR & 0X0008;}
/*-------------------*/
/*-------------------IOPA4/CAP2/QEP1*/
/*使能通用或特殊功能管脚宏*/
#define ENABLE_IOPA4_PIN OCRA &=~0X0010;
#define DISABLE_IOPA4_PIN OCRA |= 0X0010;
#define ENABLE_CAP2_PIN DISABLE_IOPA4_PIN;
#define DISABLE_CAP2_PIN ENABLE_IOPA4_PIN;
#define ENABLE_QEP1_PIN DISABLE_IOPA4_PIN;
#define DISABLE_QEP1_PIN ENABLE_IOPA4_PIN;
/*设置通用管脚为输出并设置电瓶宏*/
#define ENABLE_IOPA4_OUTPIN {ENABLE_IOPA4_PIN; PADATDIR |= 0X1000;}
#define SET_IOPA4_OUTPIN {ENABLE_IOPA4_OUTPIN; PADATDIR |= 0X0010;}
#define CLR_IOPA4_OUTPIN {ENABLE_IOPA4_OUTPIN; PADATDIR &=~0X0010;}
#define SWITCH_IOPA4_OUTPIN {ENABLE_IOPA4_OUTPIN; PADATDIR ^= 0X0010;}
/*设置通用管脚为输入并读状态宏*/
#define ENABLE_IOPA4_INPIN {ENABLE_IOPA4_PIN; PADATDIR &=~0X1000;}
#define READ_IOPA4_INPIN(var) {var = PADATDIR & 0X0010;}
/*-------------------*/
/*-------------------IOPA5/CAP3/
/*使能通用或特殊功能管脚宏*/
#define ENABLE_IOPA5_PIN OCRA &=~0X0020;
#define DISABLE_IOPA5_PIN OCRA |= 0X0020;
#define ENABLE_CAP3_PIN DISABLE_IOPA5_PIN;
#define DISABLE_CAP3_PIN ENABLE_IOPA5_PIN;
/*设置通用管脚为输出并设置电瓶宏*/
#define ENABLE_IOPA5_OUTPIN {ENABLE_IOPA5_PIN; PADATDIR |= 0X2000;}
#define SET_IOPA5_OUTPIN {ENABLE_IOPA5_OUTPIN; PADATDIR |= 0X0020;}
#define CLR_IOPA5_OUTPIN {ENABLE_IOPA5_PIN; ENABLE_IOPA5_OUTPIN; PADATDIR &=~0X0020;}
#define SWITCH_IOPA5_OUTPIN {ENABLE_IOPA5_PIN; ENABLE_IOPA5_OUTPIN; PADATDIR ^= 0X0020;}
/*设置通用管脚为输入并读状态宏*/
#define ENABLE_IOPA5_INPIN {ENABLE_IOPA5_PIN; PADATDIR &=~0X2000;}
#define READ_IOPA5_INPIN(var) {var = PADATDIR & 0X0020;}
/*-------------------*/
/*-------------------IOPC0/W/R*/
/*使能通用或特殊功能管脚宏*/
#define ENABLE_IOPC0_PIN OCRB &=~0X0001;
#define DISABLE_IOPC0_PIN OCRB |= 0X0001;
#define ENABLE_W-R_PIN DISABLE_IOPC0_PIN;
#define DISABLE_W-R_PIN ENABLE_IOPC0_PIN;
/*设置通用管脚为输出并设置电瓶宏*/
#define ENABLE_IOPC0_OUTPIN {ENABLE_IOPC0_PIN; PCDATDIR |= 0X0100;}
#define SET_IOPC0_OUTPIN {ENABLE_IOPC0_OUTPIN; PCDATDIR |= 0X0001;}
#define CLR_IOPC0_OUTPIN {ENABLE_IOPC0_OUTPIN; PCDATDIR &=~0X0001;}
#define SWITCH_IOPC0_OUTPIN {ENABLE_IOPC0_OUTPIN; PCDATDIR ^= 0X0001;}
/*设置通用管脚为输入并读状态宏*/
#define ENABLE_IOPC0_INPIN {ENABLE_IOPC0_PIN; PCDATDIR &=~0X0100;}
#define READ_IOPC0_INPIN(var) {var = PCDATDIR & 0X0001;}
/*-------------------*/
/*-------------------IOPC4/SPICLK*/
/*使能通用或特殊功能管脚宏*/
#define ENABLE_IOPC4_PIN OCRB &=~0X0010;
#define DISABLE_IOPC4_PIN OCRB |= 0X0010;
#define ENABLE_SPICLK_PIN DISABLE_IOPC4_PIN;
#define DISABLE_SPICLK_PIN ENABLE_IOPC4_PIN;
/*设置通用管脚为输出并设置电瓶宏*/
#define ENABLE_IOPC4_OUTPIN {ENABLE_IOPC4_PIN; PCDATDIR |= 0X1000;}
#define SET_IOPC4_OUTPIN {ENABLE_IOPC4_OUTPIN; PCDATDIR |= 0X0010;}
#define CLR_IOPC4_OUTPIN {ENABLE_IOPC4_OUTPIN; PCDATDIR &=~0X0010;}
#define SWITCH_IOPC4_OUTPIN {ENABLE_IOPC4_OUTPIN; PCDATDIR ^= 0X0010;}
/*设置通用管脚为输入并读状态宏*/
#define ENABLE_IOPC4_INPIN {ENABLE_IOPC4_PIN; PCDATDIR &=~0X1000;}
#define READ_IOPC4_INPIN(var) {var = PCDATDIR & 0X0010;}
/*-------------------*/⌨️ 快捷键说明
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