a8251.map.rpt

8251芯片功能的vhdl描述

; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto DSP Block Replacement                                         ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto RAM Block Balancing                                           ; On                 ; On                 ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M512 Memory Blocks                               ; Unlimited          ; Unlimited          ;
; Maximum Number of M4K Memory Blocks                                ; Unlimited          ; Unlimited          ;
; Maximum Number of M-RAM Memory Blocks                              ; Unlimited          ; Unlimited          ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                       ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                          ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------------+
; addr_latch.vhd                   ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/addr_latch.vhd    ;
; data_latch.vhd                   ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/data_latch.vhd    ;
; dout_mux.vhd                     ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/dout_mux.vhd      ;
; Proc.vhd                         ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Proc.vhd          ;
; Proc_cmd_reg.vhd                 ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Proc_cmd_reg.vhd  ;
; PROC_DEC.VHD                     ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/PROC_DEC.VHD      ;
; Proc_mode_reg.vhd                ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Proc_mode_reg.vhd ;
; Proc_sm.vhd                      ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Proc_sm.vhd       ;
; Proc_sync_reg.vhd                ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Proc_sync_reg.vhd ;
; Rx.vhd                           ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Rx.vhd            ;
; Rx_break_cnt.vhd                 ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Rx_break_cnt.vhd  ;
; Rx_cntrl.vhd                     ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Rx_cntrl.vhd      ;
; Rx_cntrl_cnt.vhd                 ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Rx_cntrl_cnt.vhd  ;
; Rx_cntrl_sm.vhd                  ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Rx_cntrl_sm.vhd   ;
; Rx_data_cnt.vhd                  ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Rx_data_cnt.vhd   ;
; Rx_data_reg.vhd                  ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Rx_data_reg.vhd   ;
; Rx_det_cntrl.vhd                 ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Rx_det_cntrl.vhd  ;
; Rx_error_reg.vhd                 ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Rx_error_reg.vhd  ;
; Rx_par_tree.vhd                  ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Rx_par_tree.vhd   ;
; Rx_ready_reg.vhd                 ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Rx_ready_reg.vhd  ;
; Rx_shift_reg.vhd                 ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Rx_shift_reg.vhd  ;
; Rx_sync_comp.vhd                 ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Rx_sync_comp.vhd  ;
; Rx_sync_stat.vhd                 ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Rx_sync_stat.vhd  ;
; Tx.vhd                           ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Tx.vhd            ;
; Tx_clk_div.vhd                   ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Tx_clk_div.vhd    ;
; Tx_cntrl.vhd                     ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Tx_cntrl.vhd      ;
; Tx_data_cnt.vhd                  ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Tx_data_cnt.vhd   ;
; Tx_data_mux.vhd                  ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Tx_data_mux.vhd   ;
; Tx_fifo.vhd                      ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Tx_fifo.vhd       ;
; Tx_line_mux.vhd                  ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Tx_line_mux.vhd   ;
; Tx_par_gen.vhd                   ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Tx_par_gen.vhd    ;
; Tx_shift_reg.vhd                 ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Tx_shift_reg.vhd  ;
; Tx_state_mach.vhd                ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/Tx_state_mach.vhd ;
; wr_ext.vhd                       ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/wr_ext.vhd        ;
; A8251.vhd                        ; yes             ; User VHDL File  ; G:/design/summer work/download/8251/A8251.vhd         ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 530   ;
;     -- Combinational with no register       ; 374   ;
;     -- Register only                        ; 44    ;
;     -- Combinational with a register        ; 112   ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 288   ;
;     -- 3 input functions                    ; 110   ;
;     -- 2 input functions                    ; 84    ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 3     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 506   ;
;     -- arithmetic mode                      ; 24    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 52    ;
;     -- asynchronous clear/load mode         ; 156   ;
;                                             ;       ;
; Total registers                             ; 156   ;
; Total logic cells in carry chains           ; 28    ;
; I/O pins                                    ; 36    ;
; Maximum fan-out node                        ; reset ;
; Maximum fan-out                             ; 187   ;
; Total fan-out                               ; 2124  ;
; Average fan-out                             ; 3.75  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                        ;
+------------------------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------+
; Compilation Hierarchy Node               ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                              ;
+------------------------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------+
; |a8251                                   ; 530 (9)     ; 156          ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 36   ; 0            ; 374 (9)      ; 44 (0)            ; 112 (0)          ; 28 (0)          ; 0 (0)      ; |a8251                                                           ;
;    |AddrLatch:i_AddrSync|                ; 1 (1)       ; 0            ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |a8251|AddrLatch:i_AddrSync                                      ;
;    |DataLatch:i_DataSync|                ; 8 (8)       ; 0            ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |a8251|DataLatch:i_DataSync                                      ;
;    |Wr_Ext:i_Wr_Ext|                     ; 2 (2)       ; 1            ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 1 (1)            ; 0 (0)           ; 0 (0)      ; |a8251|Wr_Ext:i_Wr_Ext                                           ;
;    |dout_mux:i_dout_mux|                 ; 8 (8)       ; 0            ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |a8251|dout_mux:i_dout_mux                                       ;