a8251.map.rpt

8251芯片功能的vhdl描述

Analysis & Synthesis report for A8251
Sun Jul 15 17:48:42 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. State Machine - |a8251|tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|state
  8. State Machine - |a8251|rx:i_rx|rx_det_cntrl:i_rx_det_cntrl|state
  9. State Machine - |a8251|rx:i_rx|rx_cntrl:i_rx_cntrl|rx_cntrl_sm:i_rx_cntrlsm|state
 10. State Machine - |a8251|proc:i_procintf|proc_sm:I_proc_sm|state
 11. User-Specified and Inferred Latches
 12. General Register Statistics
 13. Inverted Register Statistics
 14. Multiplexer Restructuring Statistics (No Restructuring Performed)
 15. Source assignments for proc:i_procintf|proc_sm:I_proc_sm
 16. Source assignments for rx:i_rx|rx_cntrl:i_rx_cntrl|rx_cntrl_sm:i_rx_cntrlsm
 17. Source assignments for rx:i_rx|rx_cntrl:i_rx_cntrl|rx_cntrl_cnt:i_rx_cntrl_cnt
 18. Source assignments for rx:i_rx|rx_det_cntrl:i_rx_det_cntrl
 19. Source assignments for rx:i_rx|rx_shift_reg:i_rx_shift_reg
 20. Source assignments for rx:i_rx|rx_data_cnt:i_rx_data_cnt
 21. Source assignments for rx:i_rx|rx_break_cnt:i_rx_break_cnt
 22. Source assignments for tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach
 23. Source assignments for tx:i_tx|tx_cntrl:i_tx_cntrl|tx_data_cnt:i_tx_data_cnt
 24. Source assignments for tx:i_tx|tx_cntrl:i_tx_cntrl|tx_clk_div:i_tx_clk_div
 25. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Jul 15 17:48:42 2007    ;
; Quartus II Version          ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name               ; A8251                                    ;
; Top-level Entity Name       ; a8251                                    ;
; Family                      ; Stratix                                  ;
; Total logic elements        ; 530                                      ;
; Total pins                  ; 36                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 0                                        ;
; DSP block 9-bit elements    ; 0                                        ;
; Total PLLs                  ; 0                                        ;
; Total DLLs                  ; 0                                        ;
+-----------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP1S25F780C6       ;                    ;
; Top-level entity name                                              ; A8251              ; A8251              ;
; Family name                                                        ; Stratix            ; Stratix            ;
; Optimization Technique -- Stratix/Stratix GX                       ; Speed              ; Balanced           ;
; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; Maximum DSP Block Usage                                            ; Unlimited          ; Unlimited          ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Remove Duplicate Logic                                             ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;