a8251.fit.qmsg

8251芯片功能的vhdl描述

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.986 ns register register " "Info: Estimated most critical path is register to register delay of 6.986 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|data\[6\] 1 REG LAB_X44_Y37 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X44_Y37; Fanout = 7; REG Node = 'rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|data\[6\]'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { rx:i_rx|rx_shift_reg:i_rx_shift_reg|data[6] } "NODE_NAME" } } { "Rx_shift_reg.vhd" "" { Text "G:/design/summer work/download/8251/Rx_shift_reg.vhd" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.332 ns) 0.765 ns rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|par_out~4175 2 COMB LAB_X45_Y37 2 " "Info: 2: + IC(0.433 ns) + CELL(0.332 ns) = 0.765 ns; Loc. = LAB_X45_Y37; Fanout = 2; COMB Node = 'rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|par_out~4175'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.765 ns" { rx:i_rx|rx_shift_reg:i_rx_shift_reg|data[6] rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out~4175 } "NODE_NAME" } } { "Rx_shift_reg.vhd" "" { Text "G:/design/summer work/download/8251/Rx_shift_reg.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.055 ns) + CELL(0.459 ns) 1.279 ns rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|par_out~4177 3 COMB LAB_X45_Y37 1 " "Info: 3: + IC(0.055 ns) + CELL(0.459 ns) = 1.279 ns; Loc. = LAB_X45_Y37; Fanout = 1; COMB Node = 'rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|par_out~4177'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.514 ns" { rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out~4175 rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out~4177 } "NODE_NAME" } } { "Rx_shift_reg.vhd" "" { Text "G:/design/summer work/download/8251/Rx_shift_reg.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.087 ns) 1.793 ns rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|par_out~4178 4 COMB LAB_X45_Y37 2 " "Info: 4: + IC(0.427 ns) + CELL(0.087 ns) = 1.793 ns; Loc. = LAB_X45_Y37; Fanout = 2; COMB Node = 'rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|par_out~4178'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.514 ns" { rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out~4177 rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out~4178 } "NODE_NAME" } } { "Rx_shift_reg.vhd" "" { Text "G:/design/summer work/download/8251/Rx_shift_reg.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.055 ns) + CELL(0.459 ns) 2.307 ns rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|par_out\[2\]~4180 5 COMB LAB_X45_Y37 4 " "Info: 5: + IC(0.055 ns) + CELL(0.459 ns) = 2.307 ns; Loc. = LAB_X45_Y37; Fanout = 4; COMB Node = 'rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|par_out\[2\]~4180'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.514 ns" { rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out~4178 rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[2]~4180 } "NODE_NAME" } } { "Rx_shift_reg.vhd" "" { Text "G:/design/summer work/download/8251/Rx_shift_reg.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.488 ns) + CELL(0.213 ns) 3.008 ns rx:i_rx\|rx_sync_comp:i_rx_sync_comp\|Equal4~245 6 COMB LAB_X44_Y37 1 " "Info: 6: + IC(0.488 ns) + CELL(0.213 ns) = 3.008 ns; Loc. = LAB_X44_Y37; Fanout = 1; COMB Node = 'rx:i_rx\|rx_sync_comp:i_rx_sync_comp\|Equal4~245'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.701 ns" { rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[2]~4180 rx:i_rx|rx_sync_comp:i_rx_sync_comp|Equal4~245 } "NODE_NAME" } } { "Rx_sync_comp.vhd" "" { Text "G:/design/summer work/download/8251/Rx_sync_comp.vhd" 109 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.136 ns) + CELL(0.087 ns) 4.231 ns rx:i_rx\|rx_sync_comp:i_rx_sync_comp\|Equal4~246 7 COMB LAB_X43_Y38 2 " "Info: 7: + IC(1.136 ns) + CELL(0.087 ns) = 4.231 ns; Loc. = LAB_X43_Y38; Fanout = 2; COMB Node = 'rx:i_rx\|rx_sync_comp:i_rx_sync_comp\|Equal4~246'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.223 ns" { rx:i_rx|rx_sync_comp:i_rx_sync_comp|Equal4~245 rx:i_rx|rx_sync_comp:i_rx_sync_comp|Equal4~246 } "NODE_NAME" } } { "Rx_sync_comp.vhd" "" { Text "G:/design/summer work/download/8251/Rx_sync_comp.vhd" 109 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.603 ns) + CELL(0.459 ns) 5.293 ns rx:i_rx\|rx_sync_comp:i_rx_sync_comp\|Equal4~251 8 COMB LAB_X48_Y38 3 " "Info: 8: + IC(0.603 ns) + CELL(0.459 ns) = 5.293 ns; Loc. = LAB_X48_Y38; Fanout = 3; COMB Node = 'rx:i_rx\|rx_sync_comp:i_rx_sync_comp\|Equal4~251'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.062 ns" { rx:i_rx|rx_sync_comp:i_rx_sync_comp|Equal4~246 rx:i_rx|rx_sync_comp:i_rx_sync_comp|Equal4~251 } "NODE_NAME" } } { "Rx_sync_comp.vhd" "" { Text "G:/design/summer work/download/8251/Rx_sync_comp.vhd" 109 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.332 ns) 5.807 ns rx:i_rx\|rx_det_cntrl:i_rx_det_cntrl\|Selector0~141 9 COMB LAB_X48_Y38 3 " "Info: 9: + IC(0.182 ns) + CELL(0.332 ns) = 5.807 ns; Loc. = LAB_X48_Y38; Fanout = 3; COMB Node = 'rx:i_rx\|rx_det_cntrl:i_rx_det_cntrl\|Selector0~141'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.514 ns" { rx:i_rx|rx_sync_comp:i_rx_sync_comp|Equal4~251 rx:i_rx|rx_det_cntrl:i_rx_det_cntrl|Selector0~141 } "NODE_NAME" } } { "Rx_det_cntrl.vhd" "" { Text "G:/design/summer work/download/8251/Rx_det_cntrl.vhd" 138 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.301 ns) + CELL(0.213 ns) 6.321 ns rx:i_rx\|rx_cntrl:i_rx_cntrl\|rx_cntrl_sm:i_rx_cntrlsm\|Selector4~52 10 COMB LAB_X48_Y38 1 " "Info: 10: + IC(0.301 ns) + CELL(0.213 ns) = 6.321 ns; Loc. = LAB_X48_Y38; Fanout = 1; COMB Node = 'rx:i_rx\|rx_cntrl:i_rx_cntrl\|rx_cntrl_sm:i_rx_cntrlsm\|Selector4~52'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.514 ns" { rx:i_rx|rx_det_cntrl:i_rx_det_cntrl|Selector0~141 rx:i_rx|rx_cntrl:i_rx_cntrl|rx_cntrl_sm:i_rx_cntrlsm|Selector4~52 } "NODE_NAME" } } { "Rx_cntrl_sm.vhd" "" { Text "G:/design/summer work/download/8251/Rx_cntrl_sm.vhd" 168 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.301 ns) + CELL(0.364 ns) 6.986 ns rx:i_rx\|rx_cntrl:i_rx_cntrl\|rx_cntrl_sm:i_rx_cntrlsm\|state.sync_det 11 REG LAB_X48_Y38 4 " "Info: 11: + IC(0.301 ns) + CELL(0.364 ns) = 6.986 ns; Loc. = LAB_X48_Y38; Fanout = 4; REG Node = 'rx:i_rx\|rx_cntrl:i_rx_cntrl\|rx_cntrl_sm:i_rx_cntrlsm\|state.sync_det'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.665 ns" { rx:i_rx|rx_cntrl:i_rx_cntrl|rx_cntrl_sm:i_rx_cntrlsm|Selector4~52 rx:i_rx|rx_cntrl:i_rx_cntrl|rx_cntrl_sm:i_rx_cntrlsm|state.sync_det } "NODE_NAME" } } { "Rx_cntrl_sm.vhd" "" { Text "G:/design/summer work/download/8251/Rx_cntrl_sm.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.005 ns ( 43.01 % ) " "Info: Total cell delay = 3.005 ns ( 43.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.981 ns ( 56.99 % ) " "Info: Total interconnect delay = 3.981 ns ( 56.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "6.986 ns" { rx:i_rx|rx_shift_reg:i_rx_shift_reg|data[6] rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out~4175 rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out~4177 rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out~4178 rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[2]~4180 rx:i_rx|rx_sync_comp:i_rx_sync_comp|Equal4~245 rx:i_rx|rx_sync_comp:i_rx_sync_comp|Equal4~246 rx:i_rx|rx_sync_comp:i_rx_sync_comp|Equal4~251 rx:i_rx|rx_det_cntrl:i_rx_det_cntrl|Selector0~141 rx:i_rx|rx_cntrl:i_rx_cntrl|rx_cntrl_sm:i_rx_cntrlsm|Selector4~52 rx:i_rx|rx_cntrl:i_rx_cntrl|rx_cntrl_sm:i_rx_cntrlsm|state.sync_det } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 3 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 3%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x45_y36 x56_y47 " "Info: The peak interconnect region extends from location x45_y36 to location x56_y47" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:08 " "Info: Fitter routing operations ending: elapsed time is 00:00:08" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "reset " "Info: Node reset uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear proc:i_procintf\|proc_mode_reg:I_proc_mode_reg\|int_dout\[2\] " "Info: Port clear -- assigned as a global for destination node proc:i_procintf\|proc_mode_reg:I_proc_mode_reg\|int_dout\[2\] -- routed using non-global resources" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { proc:i_procintf|proc_mode_reg:I_proc_mode_reg|int_dout[2] } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/altera1/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "proc:i_procintf\|proc_mode_reg:I_proc_mode_reg\|int_dout\[2\]" } } } } { "Proc_mode_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_mode_reg.vhd" 100 -1 0 } } { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { proc:i_procintf|proc_mode_reg:I_proc_mode_reg|int_dout[2] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear proc:i_procintf\|proc_mode_reg:I_proc_mode_reg\|int_dout\[3\] " "Info: Port clear -- assigned as a global for destination node proc:i_procintf\|proc_mode_reg:I_proc_mode_reg\|int_dout\[3\] -- routed using non-global resources" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { proc:i_procintf|proc_mode_reg:I_proc_mode_reg|int_dout[3] } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/altera1/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "proc:i_procintf\|proc_mode_reg:I_proc_mode_reg\|int_dout\[3\]" } } } } { "Proc_mode_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_mode_reg.vhd" 100 -1 0 } } { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { proc:i_procintf|proc_mode_reg:I_proc_mode_reg|int_dout[3] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear proc:i_procintf\|proc_mode_reg:I_proc_mode_reg\|int_dout\[4\] " "Info: Port clear -- assigned as a global for destination node proc:i_procintf\|proc_mode_reg:I_proc_mode_reg\|int_dout\[4\] -- routed using non-global resources" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { proc:i_procintf|proc_mode_reg:I_proc_mode_reg|int_dout[4] } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/altera1/quartus6.0/win/Assignment Editor.qase" 1 { {